IP Library › Granted Patent US 8,120,405
Granted Patent B1
US 8,120,405 · App. 11/419,454 · Granted Feb 21, 2012

Method and apparatus for an output buffer with dynamic impedance control

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Quick Facts
Patent No.
US 8,120,405
App. No.
11/419,454
Granted
Feb 21, 2012
Kind
B1
Abstract

A method and apparatus for an output buffer with dynamic impedance control have been disclosed.

Claims (6)

1. A method comprising:

generating an output signal from a node of two stacked P-type transistors and two stacked N-type transistors;

receiving said output signal;

feeding back a first signal based on said received output signal by passing said received output signal through a P-type transistor connected to at least one transistor in said two stacked P-type transistors; and

feeding back a second signal based on said received output signal by passing said received output signal through a N-type transistor connected to at least one transistor in said two stacked N-type transistors.

2. The method of claim 1 wherein said feeding back further comprises a comparison of said received output signal to a reference voltage.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →