DRAM interface circuits that support fast deskew calibration and methods of operating same
View Patent ↗A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.
1. An integrated circuit device, comprising:
a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals of equivalent frequency received at an interface of the integrated circuit device; and
a data capture circuit configured to capture a plurality of data streams associated with the plurality of data strobe signals, said data capture circuit comprising:
a skew control circuit responsive to the skew data, said skew control circuit configured to determine a fast skew limit in response to identifying a second internal clock signal having a relatively slow skew when compared to a first internal clock signal having a relatively fast skew and further configured to reduce a skew difference between a first data stream associated with the first internal clock signal and a second data stream associated with the second internal clock signal by capturing the first data stream in-sync with a phase-delayed version of the first internal clock signal having a skew that lags the fast skew limit.
2. The integrated circuit device of claim 1 , wherein said skew control circuit is configured to identify the second internal clock signal as a clock signal having the greatest lagging skew relative to the first internal clock signal.
3. The integrated circuit device of claim 2 , wherein said skew control circuit is configured to determine the fast skew limit as a limit that is 180° in advance of the second internal clock signal.
4. The integrated circuit device of claim 3 , wherein said skew control circuit is configured to delay a skew of all of the plurality of internal clock signals having skews in advance of the fast skew limit by 180°.
5. The integrated circuit device of claim 1 , wherein said skew control circuit determines the fast skew limit by identifying a slowest one of the plurality of internal clock signals based on the skew data and measuring a fixed number of degrees in advance of the skew associated with the slowest one of the plurality of internal clock signals.
6. The integrated circuit device of claim 5 , wherein said skew control circuit is further configured to identify each of the plurality of internal clock signals having a skew in advance of the fast skew limit and generate phase-delayed versions of each of the plurality of internal clock signals identified as having a skew in advance of the fast skew limit.
7. The integrated circuit device of claim 6 , wherein the phase-delayed versions of each of the plurality of internal clock signals identified as having a skew in advance of the fast skew limit all have skews that lag the fast skew limit.
8. An integrated circuit device, comprising:
a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals of equivalent frequency received at an interface of the integrated circuit device; and
a data capture circuit configured to capture a plurality of data streams associated with the plurality of data strobe signals, said data capture circuit comprising:
a skew control circuit responsive to the skew data, said skew control circuit configured to identify a slowest one of the plurality of internal clock signals and further configured to reduce a skew difference between a first data stream associated with first one of the plurality of internal clock signals and a second data stream associated with the slowest one of the plurality of internal clock signals by capturing the first data stream in-sync with a phase-delayed version of the first one of the plurality of internal clock signals.
9. A method of reducing skew between a plurality of data streams, comprising the steps of:
determining skews between a plurality of clock signals having equivalent frequency;
identifying a slowest one of the plurality of clock signals;
determining a fast skew limit relative to the slowest one of the plurality of clock signals;
identifying a first one of the plurality of clock signals having a skew that is faster than the slowest one of the plurality of clock signals by a skew amount greater than the fast skew limit;
capturing first data synchronized with the slowest one of the plurality of clock signals; and
capturing second data synchronized with a delayed version of the first one of the plurality of clock signals having a skew less than the fast skew limit.