IP Library Granted Patent US 8,426,233
Granted Patent B1
US 8,426,233 · App. 13/077,312 · Granted Apr 23, 2013

Methods of packaging microelectromechanical resonators

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Quick Facts
Patent No.
US 8,426,233
App. No.
13/077,312
Granted
Apr 23, 2013
Kind
B1
Abstract

Methods of forming packaged microelectromechanical resonators include forming a first isolation trench in a first surface of a capping substrate, with the first isolation trench encircling a first portion of the capping substrate. The first isolation trench is filled with an electrically insulating material. The first surface of the capping substrate is bonded to a device substrate, which includes the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator. A second surface of the capping substrate is planarized for a sufficient duration to thereby expose the electrically insulating material and the first portion of the capping substrate encircled by the first isolation trench. The exposed first portion of the capping substrate is selectively etched to thereby define a through-substrate opening therein, which exposes a first portion of the first electrically conductive line. At least a portion of the through-substrate opening is filled with an electrically conductive through-substrate via, which is electrically connected to the first portion of the first electrically conductive line.

Claims (47)

1. A method of forming a packaged microelectromechanical resonator, comprising:

forming a first isolation trench in a first surface of a capping substrate, said first isolation trench encircling a first portion of the capping substrate;

filling the first isolation trench with an electrically insulating material;

bonding the first surface of the capping substrate to a device substrate comprising the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator;

selectively etching through the first portion of the capping substrate to thereby define a through-substrate opening therein that exposes a first portion of the first electrically conductive line; and

filling at least a portion of the through-substrate opening with an electrically conductive through-substrate via that is electrically connected to the first portion of the first electrically conductive line.

2. The method of claim 1 , wherein said filling at least a portion of the through-substrate opening comprises depositing a metal layer into the through-substrate opening and onto an upper surface of the dielectric layer and then patterning the deposited metal layer to thereby define a first bond pad on the dielectric layer.

3. The method of claim 1 , wherein the first isolation trench is a ring-shaped trench that encircles the first portion of the capping substrate.

4. The method of claim 1 , wherein the first isolation trench is a square ring-shaped trench that encircles the first portion of the capping substrate.

5. A method of forming a packaged microelectromechanical resonator, comprising:

forming a first isolation trench in a first surface of a capping substrate, said first isolation trench encircling a first portion of the capping substrate;

filling the first isolation trench with an electrically insulating material;

bonding the first surface of the capping substrate to a device substrate comprising the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator;

selectively etching a second isolation trench in a second surface of the capping substrate to thereby expose the electrically insulating material at a bottom of the first isolation trench, said second isolation trench encircling a second portion of the capping substrate; and

depositing an electrically insulating dielectric layer on the second surface of the capping substrate and into the second isolation trench, said electrically insulating dielectric layer contacting the electrically insulating material at the bottom of the first isolation trench;

selectively etching through the first portion of the capping substrate to thereby define a through-substrate opening therein that exposes a first portion of the first electrically conductive line; and

filling at least a portion of the through-substrate opening with an electrically conductive through-substrate via that is electrically connected to the first portion of the first electrically conductive line.

6. The method of claim 5 , wherein said selectively etching through the first portion of the capping substrate comprises selectively etching through the dielectric layer, the second portion of the capping substrate and the first portion of the capping substrate to thereby define the through-substrate opening.

7. The method of claim 6 , wherein said filling comprises depositing a metal layer into the through-substrate opening and on an upper surface of the dielectric layer and then patterning the deposited metal layer to thereby define a first bond pad on the dielectric layer.

8. The method of claim 5 , wherein the first isolation trench is a ring-shaped trench that encircles the first portion of the capping substrate.

9. The method of claim 5 , wherein the first isolation trench is a square ring-shaped trench that encircles the first portion of the capping substrate.

10. A method of forming a packaged microelectromechanical resonator, comprising:

forming a first isolation trench in a first surface of a semiconductor-on-insulator (SOI) capping substrate comprising a semiconductor capping layer on a buried insulating layer, said first isolation trench encircling a first portion of the semiconductor capping layer and exposing the buried insulating layer;

filling the first isolation trench with an electrically insulating material;

bonding the first surface of the SOI capping substrate to a device substrate comprising the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator;

planarizing a second surface of the SOI capping substrate for a sufficient duration to thereby expose the buried insulating layer;

selectively etching through the buried insulating layer and the first portion of the semiconductor capping layer to thereby define a through-substrate opening therein that exposes a first portion of the first electrically conductive line; and

filling at least a portion of the through-substrate opening with an electrically conductive through-substrate via that is electrically connected to the first portion of the first electrically conductive line.

11. The method of claim 10 , wherein said filling comprises depositing a metal layer into the through-substrate opening and onto an upper surface of the exposed buried insulating layer and then patterning the deposited metal layer to thereby define a first bond pad on the buried insulating layer.

12. The method of claim 10 , wherein said bonding is preceded by forming a polymer bonding layer on the first surface of the SOI capping substrate; and wherein said bonding comprises bonding the polymer bonding layer directly to the device substrate.

13. A method of forming a packaged microelectromechanical resonator, comprising:

forming a first isolation trench in a first surface of a capping substrate, said first isolation trench encircling a first portion of the capping substrate;

filling the first isolation trench with an electrically insulating material;

bonding the first surface of the capping substrate to a device substrate comprising the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator;

planarizing a second surface of the capping substrate;

selectively etching through the first portion of the capping substrate to thereby define a through-substrate opening therein that exposes a first portion of the first electrically conductive line; and

filling at least a portion of the through-substrate opening with an electrically conductive through-substrate via that is electrically connected to the first portion of the first electrically conductive line.

14. The method of claim 13 , wherein said selectively etching is preceded by depositing an electrically insulating dielectric layer on the planarized second surface of the capping substrate; and wherein said selectively etching comprises selectively etching through the dielectric layer and the first portion of the capping substrate to thereby define the through-substrate opening.

15. The method of claim 13 , wherein the first isolation trench is a ring-shaped trench that encircles the first portion of the capping substrate.

16. The method of claim 13 , wherein the first isolation trench is a square ring-shaped trench that encircles the first portion of the capping substrate.

17. A method of forming a packaged microelectromechanical resonator, comprising:

forming a first isolation trench in a first surface of a capping substrate, said first isolation trench encircling a first portion of the capping substrate;

filling the first isolation trench with an electrically insulating material;

forming a polymer bonding layer on the first surface of the capping substrate; bonding the polymer bonding layer directly to a device substrate comprising the microelectromechanical resonator and at least a first electrically conductive line connected to the microelectromechanical resonator;

selectively etching through the first portion of the capping substrate to thereby define a through-substrate opening therein that exposes a first portion of the first electrically conductive line; and

filling at least a portion of the through-substrate opening with an electrically conductive through-substrate via that is electrically connected to the first portion of the first electrically conductive line.

18. The method of claim 17 , wherein the first isolation trench is a ring-shaped trench that encircles the first portion of the capping substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2011
From: LEI, KUOLUNG; PAI, MINFAN; PAN, WANLING
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 026101/0706 →