Single-ended signal slicer with a wide input voltage range

1. An apparatus comprising:

a first circuit configured to (i) reduce a current value in a sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel to generate a reduced version of said current value, and (ii) reduce a first reference voltage to generate a second reference voltage;

a second circuit configured to slice said current value with respect to said first reference voltage to generate a first intermediate value; and

a third circuit configured to slice said reduced version of said current value with respect to said second reference voltage to generate a second intermediate value, wherein said first intermediate value and said second intermediate value define a sliced value of said current value.

2. The apparatus according to claim 1 , further comprising a fourth circuit configured to latch said sliced value of said current value in response to said first intermediate value and said second intermediate value.

3. The apparatus according to claim 2 , wherein (i) said first circuit comprises a plurality of transmission gates in a registered clock driver (RCD) circuit, (ii) said second circuit comprises a first slicer with NMOS input transistors in said RCD circuit, (iii) said third circuit comprises a second slicer with PMOS input transistors in said RCD circuit, and (iv) said fourth circuit comprises a latch in said RCD circuit.

4. The apparatus according to claim 3 , wherein said RCD circuit is at least double data rate fourth generation (DDR4) compliant.

5. The apparatus according to claim 1 , wherein (i) said first circuit, said sequence of input values, and said first reference voltage are in a first voltage domain, (ii) said second circuit and said third circuit operate in a second voltage domain, and (iii) said first voltage domain has a higher voltage range than said second voltage domain.

6. The apparatus according to claim 1 , wherein (i) said first circuit comprises a plurality of voltage clamps configured to receive said sequence of input values and said first reference voltage, and (ii) a plurality of NMOS transistors configured to generate said reduced version of said current value and said second reference voltage.

7. The apparatus according to claim 1 , wherein said second circuit comprises a plurality of native transistors configured to receive said first reference voltage and said current value.

8. The apparatus according to claim 1 , wherein said third circuit comprises a plurality of PMOS transistors each with a low threshold voltage and configured to receive said second reference voltage and said reduced version of said current value, wherein said low threshold voltage is as low as one-third a power supply voltage.

9. The apparatus according to claim 1 , wherein said apparatus introduces a delay of at most 100 picoseconds.

10. The apparatus according to claim 1 , wherein said data bus is an address/command bus of a double data rate (DDR) memory module.

11. The apparatus according to claim 10 , wherein said DDR memory module comprises a double data rate fourth generation (DDR4) dual in-line memory module (DIMM).

12. A method of slicing a sequence of input values, comprising the steps of:

receiving at a circuit a first reference voltage and a current value in said sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel;

reducing said current value in said sequence of input values to generate a reduced version of said current value;

reducing said first reference voltage to generate a second reference voltage;

slicing said current value in said sequence of input values with respect to said first reference voltage to generate a first intermediate value; and

slicing said reduced version of said current value with respect to said second reference voltage to generate a second intermediate value, wherein said first intermediate value and said second intermediate value define a sliced value of said current value.

13. The method according to claim 12 , further comprising the step of:

latching said sliced value of said current value in response to said first intermediate value and said second intermediate value.

14. The method according to claim 12 , wherein (i) said sequence of input values and said first reference voltage are in a first voltage domain, (ii) said first intermediate value, said second intermediate value and said second reference voltage are in a second voltage domain, and (iii) said first voltage domain has a higher voltage range than said second voltage domain.

15. The method according to claim 12 , wherein the steps are at least double data rate fourth generation (DDR4) compliant.

16. The method according to claim 12 , wherein said current value in said sequence of input values is sliced with respect to said first reference voltage using a plurality of native transistors.

17. The method according to claim 12 , wherein (i) said reduced version of said current value is sliced with respect to said second reference voltage using a plurality of PMOS transistors each with a low threshold voltage and (ii) said low threshold voltage is as low as one-third a power supply voltage.

18. The method according to claim 12 , wherein a change in an output signal is delayed at most 100 picoseconds from an edge in a clock signal.

19. The method according to claim 12 , wherein said data bus is an address/command bus of a double data rate (DDR) memory module.

20. The method according to claim 19 , wherein said DDR memory module comprises a double data rate fourth generation (DDR4) dual in-line memory module (DIMM).