Arbitrary delay buffer
View Patent ↗A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.
1. An apparatus comprising:
a delay generator configured to provide both or select between (i) a digital delay combined with an analog delay of an input signal and (ii) the analog delay without the digital delay of the input signal.
2. The apparatus of claim 1 , wherein the digital delay comprises:
an edge detector that detects at least one of a rising edge and a falling edge (a detected edge) of the input signal;
a ring oscillator that oscillates in response to the detected edge; and
a counter that counts the number of oscillations of the ring oscillator in response to the detected edge and generates a delay signal when the count reaches a delay count that determines the duration of the oscillation.
3. The apparatus of claim 2 , wherein
the edge detector comprises a rising edge detector that detects a rising edge of the input signal and a falling edge detector that detects a falling edge of the input signal;
the ring oscillator comprises a first ring oscillator that oscillates in response to the detected rising edge and a second ring oscillator that oscillates in response to the detected falling edge; and
the counter comprises a first counter that counts a number of oscillations of the first ring oscillator and generates a first delay signal when the count reaches a first delay count and a second counter that counts the number of oscillations of the second ring oscillator and generates a second delay signal when the count reaches a second delay count.
4. The apparatus of claim 3 , further comprising:
a delayed input signal generator configured to generate a delayed version of the input signal (a delayed input signal) in response to the first and second delay signals.
5. The apparatus of claim 4 , wherein the delayed input signal generator comprises a set-reset flip flop that receives the first delay signal as a set signal and the second delay signal as a reset signal.
6. The apparatus of claim 4 , wherein the first delay count and the second delay count are programmed to maintain a duty cycle and a period of the input signal in the delayed input signal.
7. The apparatus of claim 4 , further comprising:
the analog delay configured to provide the analog delay with and without the digital delay to the input signal.
8. The apparatus of claim 7 , further comprising:
a controller that selects between application of the analog delay, the digital delay and a combination of the analog delay and the digital delay to the input signal.
9. The apparatus of claim 4 , further comprising:
a multiplexer that receives as inputs the input signal and one of the delayed input signal and the delay signal generated by the counter; and
an analog delay configured to selectively provide the analog delay to one of the input signal and the delayed input signal or delay the input signal based on the delay signal generated by the counter.
10. The apparatus of claim 2 , the ring oscillator being resettable, wherein the resettable ring oscillator comprises:
a resettable oscillator stage configured to be enabled and disabled responsive to an enable signal.
11. The apparatus of claim 10 , wherein the resettable oscillator stage comprises a voltage controlled delay line (VCDL).
12. The apparatus of claim 11 , wherein a multiplexer in the VCDL is configured to be enabled and disabled responsive to the enable signal.
13. The apparatus of claim 12 , further comprising:
a calibration circuit that calibrates a replica VCDL, which calibration is used to control the VCDL in the resettable oscillator stage.
14. A method comprising:
selecting between application of an analog delay and a combination of the analog delay and a digital delay to an input signal; and
applying the selected delay to the input signal.
15. The method of claim 14 , wherein the selection is based on a frequency of the input signal or a length of a delay applied to the input signal.
16. The method of claim 14 , wherein application of the selected delay to the input signal comprises at least one of:
applying, based on the selection, the digital delay by:
detecting at least one of a rising edge and a falling edge (a detected edge) of the input signal;
oscillating, by a ring oscillator, in response to the detected edge;
counting a number of oscillations of the ring oscillator in response to the detected edge and generating a delay signal when the count reaches a delay count; and
applying, based on the selection, the analog delay by:
applying at least one of a plurality of analog delay stages in the analog delay: (i) to the input signal, (ii) to the input signal based on the delay signal or (iii) to a delayed version of the input signal generated based on the delay signal.
17. The method of claim 16 , further comprising:
operating and resetting the ring oscillator by enabling and disabling the ring oscillator or a ring oscillator stage in the ring oscillator.
18. The method of claim 16 , further comprising:
selecting a number of the analog delay stages in the analog delay; and
selecting the delay count for the counter in the digital delay.
19. An apparatus comprising:
a digital delay configured to receive an input signal; and
an analog delay configured to selectively receive, based on a selection signal, one of the input signal and an output of the digital delay,
wherein the selection signal selects between application of one and both the analog delay and the digital delay to the input signal.
20. The apparatus of claim 19 , wherein the digital delay comprises:
an edge detector configured to receive the input signal;
a resettable ring oscillator coupled to an output of the edge detector; and
a counter coupled to an output of the resettable ring oscillator.