IP Library Granted Patent US 9,791,503
Granted Patent B1
US 9,791,503 · App. 14/871,411 · Granted Oct 17, 2017

Packaged oscillators with built-in self-test circuits that support resonator testing with reduced pin count

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,791,503
App. No.
14/871,411
Granted
Oct 17, 2017
Kind
B1
Abstract

Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test operations may occur during a built-in self-test time interval when the oscillator circuit is at least partially disabled. In this manner, built-in self-test circuitry may be utilized to provide an efficient means of testing a resonating element/structure using circuitry that is integrated within an oscillator chip and within a wafer-level chip-scale package (WLCSP) containing the resonator.

Claims (24)

1. A packaged integrated circuit device, comprising:

an oscillator circuit having a resonator associated therewith, which is configured to generate a periodic reference signal; and

a built-in self-test (BIST) circuit electrically coupled to first and second terminals of the resonator during an operation by said BIST circuit to test for a presence of at least one failure mode associated with the resonator.

2. The packaged integrated circuit device of claim 1 , wherein the operation to test for a presence of at least one failure mode is selected from a group consisting of resistance level dependency (RLD) screening and drive level dependency (DLD) screening.

3. The packaged integrated circuit device of claim 2 , wherein during the operation to test for a presence of at least one failure mode the resonator is temporarily functionally disconnected from other components of the oscillator circuit.

4. The packaged integrated circuit device of claim 3 , wherein upon completion of the operation to test for a presence of at least one failure mode, the resonator is functionally reconnected to the other components of the oscillator circuit.

5. The packaged integrated circuit device of claim 1 , wherein during the operation to test for a presence of at least one failure mode the resonator is temporarily functionally disconnected from other components of the oscillator circuit.

6. The packaged integrated circuit device of claim 1 , wherein the operation to test for a presence of at least one failure mode is commenced during an operation to power-up the oscillator circuit.

7. The packaged integrated circuit device of claim 6 , wherein during the operation to test for a presence of at least one failure mode the resonator is temporarily functionally disconnected from other components of the oscillator circuit.

8. The packaged integrated circuit device of claim 7 , wherein the BIST circuit is configured to make a go/no-go decision as to at least one performance characteristic of the resonator during the operation to test for a presence of at least one failure mode.

9. The packaged integrated circuit device of claim 6 , wherein the BIST circuit is configured to make a go/no-go decision as to at least one performance characteristic of the resonator during the operation to test for a presence of at least one failure mode.

10. The packaged integrated circuit device of claim 1 , wherein said BIST circuit is configured to make a go/no-go decision as to at least one performance characteristic of the resonator during the operation to test for a presence of at least one failure mode.

11. The packaged integrated circuit device of claim 1 , wherein the operation to test for a presence of at least one failure mode comprises measuring a first characteristic of the resonator under first test conditions and measuring a corresponding first characteristic of a reference element under otherwise equivalent first test conditions.

12. The packaged integrated circuit device of claim 11 , wherein

measuring a first characteristic of the resonator under first test conditions comprises measuring a first characteristic of the resonator under first test conditions using a first test circuit including the resonator; and wherein said measuring a corresponding first characteristic of a reference element under equivalent first test conditions comprises measuring a corresponding first characteristic of the reference element under equivalent first test conditions using the first test circuit, with the reference element replacing the resonator therein.

13. The packaged integrated circuit device of claim 12 , wherein the reference element is a resistor.

14. The packaged integrated circuit device of claim 1 , wherein the resonator is a crystal resonator containing a quartz crystal blank; and wherein the first and second terminals are input and output terminals, respectively, which are electrically connected to respective electrodes on opposing sides of the quartz crystal blank.

15. An integrated circuit device, comprising:

an oscillator circuit comprising a packaged resonating element and a built-in self-test (BIST) circuit electrically coupled to first and second terminals of the resonating element during an operation by said BIST circuit to test at least one performance characteristic of the resonating element during a built-in self-test time interval when said oscillator circuit is at least partially disabled.

16. The integrated circuit device of claim 15 , wherein during the operation by said BIST circuit to test at least one performance characteristic of the resonating element the resonating element is temporarily functionally disconnected from other components of said oscillator circuit.

17. A method of operating a packaged integrated circuit device, comprising:

testing at least one performance characteristic of a crystal resonator within the packaged integrated circuit device during a self-test time interval when the crystal resonator is electrically decoupled from oscillator circuitry within the packaged integrated circuit device;

reporting results associated with said testing to an external terminal of the packaged integrated circuit device; and

enabling operation of an oscillator circuit within the packaged integrated circuit device by electrically coupling the crystal resonator to the oscillator circuitry upon expiration of the self-test time interval.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2015
From: NORTHCUTT, JAMES BRYAN; TIBBITTS, STEPHEN AMAR; GUBSER, ROBERT A.; CLARK, BRUCE EDWARD; FALLISGAARD, JOHN WILLIAM; ASTROF, KENNETH
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 036818/0411 →