Integrated circuit memory systems having write-back buffers therein that support read-write-modify (RWM) operations within high capacity memory devices
View Patent ↗An integrated circuit memory system includes a write-back buffer and a control circuit that support read-write-modify (RWM) operations within a high capacity memory device. A RWM operation may include reading from the integrated circuit memory device and the write-back buffer to identify whether the memory device or the write-back buffer has the data requested by a read instruction issued to the memory system. The data read from the write-back buffer is then written into the memory device and a modified version of the requested data is written to the write-back buffer in anticipation of subsequent transfer to the memory device.
1. An integrated circuit memory system, comprising:
an integrated circuit memory device;
a write-back buffer; and
a control circuit configured to perform a read-write-modify (RWM) operation within the memory system by:
reading from said integrated circuit memory device and said write-back buffer to identify which one has data requested by a read request issued to the memory system;
writing data read from said write-back buffer into said integrated circuit memory device: and
writing a modified version of the requested data to said write-back buffer.
2. The memory system of claim 1 , wherein said write-back buffer and said control circuit are integrated within a memory controller chip.
3. The memory system of claim 2 , wherein said integrated circuit memory device comprises at least one dynamic random access memory (DRAM) chip.
4. The memory system of claim 3 , wherein said integrated circuit memory device and the memory controller chip are communicatively coupled together by a data bus.
5. The memory system of claim 1 , wherein reading from said integrated circuit memory device and said write-back buffer includes:
reading first data from a row in said write-back buffer designated by a row address associated with the read request; and
reading second data from a row in said integrated circuit memory device designated by the row address.
6. The memory system of claim 5 , wherein reading first data includes reading a column address associated with the first data from said write-back buffer; and wherein reading second data includes transferring a column address associated with the read request from said control circuit to said integrated circuit memory device.
7. The memory system of claim 6 , wherein said control circuit is further configured to compare the column address associated with the first data against the column address associated with the read request.
8. The memory system of claim 7 , wherein the data requested by the read request is the first data when the column address associated with the first data and the column address associated with the read request are equivalent.
9. The memory system of claim 7 , wherein the data requested by the read request is the second data when the column address associated with the first data and the column address associated with the read request are not equivalent.
10. The memory system of claim 6 , wherein writing data read from said write-back buffer into said integrated circuit memory device comprises writing the first data into the row in said integrated circuit memory device at a location specified by the column address associated with the first data.
11. The memory system of claim 10 , wherein a word line associated with the row in said integrated circuit memory device remains active without interruption during reading second data from the row in said integrated circuit memory device and writing the first data into the row said integrated circuit memory device.
12. The memory system of claim 1 , wherein writing a modified version of the requested data includes:
transferring the requested data from the memory system to a processing device external the memory system; and
transferring a modified version of the requested data from the processing device to the memory system.
13. The memory system of claim 1 , wherein each row in said write-back buffer maps one-to-one to a corresponding row in said integrated circuit memory device.
14. The memory system of claim 5 , wherein reading first data from a row in said write-back buffer includes reading a valid flag associated with the first data from said write-back buffer.
15. The memory system of claim 1 , wherein said control circuit is further configured to perform a write-back buffer initialization operation by:
reading a plurality of entries from a plurality of rows in said integrated circuit memory device; and
writing the plurality of entries read from said integrated circuit memory device into said write-back buffer.
16. An integrated circuit memory system, comprising:
an integrated circuit memory device;
a write-back buffer; and
a control circuit configured to perform a sequence of read-write-modify (RWM) operations within the memory system by:
reading first data from said integrated circuit memory device, then writing second data into said integrated circuit memory device and then modifying the first data read from said integrated circuit device; and
reading third data from said integrated circuit memory device, then writing the modified first data into said integrated circuit memory device and then modifying the third data read from said integrated circuit device.
17. The memory system of claim 16 , wherein reading first data and writing second data comprises reading first data from a first row in said integrated circuit memory device and then writing second data to the first row in said integrated circuit memory device.
18. The memory system of claim 17 , wherein writing the modified first data comprising writing the modified first data into the first row in said integrated circuit memory device.