Self-biased electrostatic discharge protection method and circuit
View Patent ↗A self-biased electrostatic discharge (ESD) protection circuit for protecting an integrated circuit operating in a normal voltage range that includes both positive and negative voltage levels is disclosed. The self-biased ESD protection circuit includes an input connection for receiving an input voltage, a protection transistor electrically coupled to the input connection, and an electrical sink. The protection transistor is operable to provide ESD protection from the input connection to the electrical sink. The self-biased ESD protection circuit also includes a metal oxide semiconductor (MOS) biasing network electrically coupled to the input connection and the protection transistor. The MOS biasing network is operable to cause the protection transistor to remain in a non-conductive state when the input voltage is in the normal operating voltage range. Upon the occurrence of an electrostatic discharge event at the input connection, the protection circuit becomes conducting to discharge ESD current from the input connection to the electrical sink.
1. A method for protecting an integrated circuit device from electrostatic discharge, the integrated circuit device operating in a normal voltage range that includes both positive and negative voltage levels, the method comprising:
providing a bipolar junction protection transistor electrically coupled to an input/output connection of the integrated circuit, the protection transistor having a collector coupled to the input/output connection, an emitter coupled to an electrical sink and a base, the protection transistor positioned to conduct an electrostatic charge between the input/output connection and the electrical sink;
biasing the protection transistor such that the protection transistor in a non-conductive state when a negative voltage within the normal operating voltage range of the integrated circuit is received at said input/output connection;
biasing the protection transistor such that the protection transistor in a non-conductive state when a positive voltage within the normal operating voltage range of the integrated circuit is received at said input/output connection; and
biasing the protection transistor such that the protection transistor conducts current to the electrical sink upon an electrostatic discharge event at the input/output connection.
2. The method for protecting an integrated circuit device from electrostatic discharge described in claim 1 , wherein the protection transistor is an NPN bipolar junction transistor, and wherein biasing the protection transistor such that the protection transistor is in a non-conductive state when a negative voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the NPN transistor such that the base voltage is substantially equal to the collector voltage, and wherein biasing the protection transistor such that the protection transistor is in a non-conductive state when a positive voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the NPN transistor such that the base voltage is substantially equal to the emitter voltage.
3. The method for protecting an integrated circuit device from electrostatic discharge described in claim 1 , wherein the protection transistor is a PNP bipolar junction transistor, and wherein the step of biasing the protection transistor such that the protection transistor is in a non-conductive state when a negative voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the PNP transistor such that the base voltage is substantially equal to the emitter voltage and wherein the step of biasing the protection transistor such that the protection transistor is in a non-conductive state when a positive voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the PNP transistor such that the base voltage is substantially equal to the collector voltage.
4. The method for protecting an integrated circuit device from electrostatic discharge described in claim 1 , wherein the electrical sink is a voltage source.
5. The method for protecting an integrated circuit device from electrostatic discharge described in claim 1 , further comprising determining whether an electrostatic discharge (ESD) event has occurred at the input/output connection by comparing the voltage at the input/output connection to a predetermined voltage and placing the protection transistor in a conducting state when the voltage at the input/output connection is greater than that of the predetermined voltage, and placing the protection transistor in a non-conductive state when the voltage at the input/output connection is less than or equal to that of the predetermined voltage.
6. The method for protecting an integrated circuit device from electrostatic discharge described in claim 1 , wherein the biasing is accomplished by a first biasing element comprising a first biasing MOSFET and a second biasing element comprising a second biasing MOSFET, the source of the first biasing MOSFET and the drain of the second biasing MOSFET electronically coupled to each other and to the base connection of the protection transistor.
7. The method for protecting an integrated circuit device from electrostatic discharge described in claim 1 , wherein the integrated circuit device comprises a multipoint low voltage differential signaling device.
8. The method of protecting an integrated circuit device of claim 1 wherein biasing the protection transistor such that the protection transistor conducts current to the electrical sink upon an electrostatic discharge event at the input/output connection further comprises biasing the protection transistor in a reversed breakdown region when the electrostatic discharge event occurs.
9. The method for protecting an integrated circuit device from electrostatic discharge described in claim 1 , wherein the electrical sink is an electrical ground.
10. A method for protecting an integrated circuit device from electrostatic discharge, the integrated circuit device operating in a normal voltage range that includes both positive and negative voltage levels the method comprising:
providing a MOS protection transistor having a drain coupled to an input/output connection, a source coupled to an electrical sink and a gate;
biasing the protection transistor such that the protection transistor is in a non-conductive state when a negative voltage within the normal operating voltage range is received at the input/output connection;
biasing the protection transistor such that the protection transistor is in a non-conductive state when a positive voltage within the normal operating voltage range is received at the input/output connection; and
biasing the protection transistor such that the protection transistor conducts current to the electrical sink upon an electrostatic discharge event at the input/output connection.
11. The method for protecting an integrated circuit device from electrostatic discharge described in claim 10 , wherein the MOS protection transistor is an NMOS transistor, and wherein the step of biasing the protection transistor such that the protection transistor is in a non-conductive state when a negative voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the NMOS transistor such that the drain voltage is substantially equal to the gate voltage and wherein the step of biasing the protection transistor such that the protection transistor is in a non-conductive state when a positive voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the NMOS transistor such that the source voltage is substantially equal to the gate voltage.
12. The method for protecting an integrated circuit device from electrostatic discharge described in claim 10 , wherein the MOS protection transistor is an PMOS transistor, and wherein the step of biasing the protection transistor such that the protection transistor is in a non-conductive state when a negative voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the PMOS transistor such that the source voltage is substantially equal to the gate voltage and wherein the step of biasing the protection transistor such that the protection transistor is in a non-conductive state when a positive voltage within the normal operating voltage range is received at the input/output connection further comprises biasing the PMOS transistor such that the drain voltage is substantially equal to the gate voltage.
13. The method for protecting an integrated circuit device from electrostatic discharge described in claim 10 , wherein the electrical sink is a voltage source.
14. The method for protecting an integrated circuit device from electrostatic discharge described in claim 10 , wherein the electrical sink is an electrical ground.
15. The method for protecting an integrated circuit device from electrostatic discharge described in claim 10 , further comprising determining whether an electrostatic discharge (ESD) event has occurred at the input/output connection by comparing the voltage at the input/output connection to a predetermined voltage and placing the protection transistor in a conducting state when the voltage at the input/output connection is greater than that of the predetermined voltage, and placing the protection transistor in a non-conductive state when the voltage at the input/output connection is less than or equal to that of the predetermined voltage.
16. The method for protecting an integrated circuit device from electrostatic discharge described in claim 10 , wherein the biasing is accomplished by a first biasing element comprising a first biasing MOSFET and a second biasing element comprising a second biasing MOSFET, the source of the first biasing MOSFET and the drain of the second biasing MOSFET electronically coupled to each other and to the base connection of the protection transistor.
17. The method for protecting an integrated circuit device from electrostatic discharge described in claim 10 , wherein the integrated circuit device comprises a multipoint low voltage differential signaling device.
18. The method of protecting an integrated circuit device of claim 10 , wherein biasing the protection transistor such that the protection transistor conducts current to the electrical sink upon an electrostatic discharge event at the input/output connection further comprises biasing the protection transistor in a reversed breakdown region when the electrostatic discharge event occurs.
19. A self-biased ESD protection circuit for protecting an integrated circuit operating in a normal voltage range that includes both positive and negative voltage levels, comprising:
an input/output connection for receiving a voltage;
a bipolar junction protection transistor electrically coupled to the input/output connection, the protection transistor having a collector coupled to the input/output connection, an emitter coupled to an electrical sink and a base, the protection transistor operable to provide electrostatic discharge (ESD) protection from the input/output connection to an electrical sink; and
a metal oxide semiconductor (MOS) biasing network electrically coupled to the input/output connection and the protection transistor, the MOS biasing network operable to bias the protection transistor in a non-conductive state when a negative voltage within the normal operating voltage range of the integrated circuit is received at the input/output connection, to bias the protection transistor in a non-conductive state when a positive voltage within the normal operating voltage range of the integrated circuit is received at the input/output connection and to bias the protection transistor to conduct current to the electrical sink upon the occurrence of an electrostatic discharge event at the input/output connection.
20. The self-biased electrostatic discharge protection circuit described in claim 19 , wherein the MOS biasing network comprises:
a first biasing element having a source electronically coupled to the base of the protection transistor and a drain electronically coupled to the input/output connection; and
a second biasing element having a drain electronically coupled to the base of the protection transistor and a source electronically coupled to the electrical sink.
21. The self-biased electrostatic discharge protection circuit described in claim 19 , wherein the electrical sink is an electrical ground.
22. The self-biased electrostatic discharge protection circuit described in claim 19 , wherein the electrical sink is a supply voltage.
23. The self-biased electrostatic discharge protection circuit described in claim 19 , wherein the protection transistor is an NPN transistor.
24. The self-biased electrostatic discharge protection circuit described in claim 19 , wherein the integrated circuit device comprises a multipoint low voltage differential signaling device.
25. The self-biased electrostatic discharge protection circuit described in claim 19 , wherein the protection transistor is a PNP transistor.
26. A self-biased ESD protection circuit for protecting an integrated circuit operating in a normal voltage range that includes both positive and negative voltage levels, comprising:
an input/output connection for receiving a voltage;
a MOS protection transistor having a drain coupled to the input/output connection, a source coupled to an electrical sink and a gate, the protection transistor operable to provide electrostatic discharge (ESD) protection from the input/output connection to an electrical sink; and
a metal oxide semiconductor (MOS) biasing network electrically coupled to the input/output connection and the protection transistor, the MOS biasing network operable to bias the protection transistor in a non-conductive state when a negative voltage within the normal operating voltage range of the integrated circuit is received at the input/output connection, to bias the protection transistor in a non-conductive state when a positive voltage within the normal operating voltage range of the integrated circuit is received at the input/output connection and to bias the protection transistor to conduct current to the electrical sink upon the occurrence of an electrostatic discharge event at the input/output connection.
27. The self-biased electrostatic discharge protection circuit described in claim 26 , wherein the MOS biasing network comprises:
a first biasing element having a source electronically coupled to the base of the protection transistor and a drain electronically coupled to the input/output connection; and
a second biasing element having a drain electronically coupled to the base of the protection transistor and a source electronically coupled to the electrical sink.
28. The self-biased electrostatic discharge protection circuit described in claim 26 , wherein the electrical sink is an electrical ground.
29. The self-biased electrostatic discharge protection circuit described in claim 26 , wherein the electrical sink is a supply voltage.
30. The self-biased electrostatic discharge protection circuit described in claim 26 , wherein the protection transistor is an NMOS transistor.
31. The self-biased electrostatic discharge protection circuit described in claim 26 , wherein protection transistor is a PMOS transistor.
32. The self-biased electrostatic discharge protection circuit described in claim 26 , wherein the integrated circuit device comprises a multipoint low voltage differential signaling device.