High frequency wireless power rectifier startup circuit design
View Patent ↗A rectifier circuit can include a plurality of FETs arranged as a rectifier; and a start-up circuit applied to each of the plurality of FETs that turn each of the FETs off during a circuit startup period, wherein the start-up circuit provides a large impedance for low power dissipation during normal operation of the rectifier.
1. A rectifier, comprising:
a first transistor and a second transistor coupled in series between a rectifier output and a ground, wherein a first AC input is coupled to a first node between the first transistor and the second transistor;
a third transistor and a fourth transistor coupled in series between the rectifier output and the ground, wherein a second AC input is coupled to a second node between the third transistor and the fourth transistor;
a first control circuit coupled between a gate of the first transistor and a gate of the fourth transistor to control operation of the first and the fourth transistors; and
a first startup circuit coupled between the gate of the first transistor and the first node, the first startup circuit controlling the gate of the first transistor in a startup time period prior to an operating period of the rectifier,
wherein the first startup circuit comprises:
a first control transistor coupled between the gate of the first transistor and the first node;
a resistive element coupled to a gate of the first control transistor; and
a second control transistor coupled between the gate of the first control transistor and the first node, a gate of the second control transistor coupled to the first control circuit, and
wherein the first control transistor is turned on by the resistive element during the startup time period and turned off by the second control transistor during the operating period.
2. The rectifier of claim 1 , further comprising
a second startup circuit coupled between the gate of the fourth transistor and the ground, the second startup circuit controlling the gate of the fourth transistor in the startup time period.
3. The rectifier of claim 1 , further comprising
a second control circuit coupled between a gate of the third transistor and a gate of the second transistor to control operation of the third and the second transistors; and
a third startup circuit coupled between the gate of the third transistor and the first node.
4. The rectifier of claim 3 , further comprising a fourth startup circuit coupled between the gate of the second transistor and the ground.
5. The rectifier of claim 1 , wherein the resistive element includes a resistor coupled between the gate of the first control transistor and a voltage node.
6. The rectifier of claim 5 , wherein the voltage node is the rectifier output.
7. The rectifier of claim 5 , further including a capacitor coupled between the gate of the first control transistor and a control node.
8. The rectifier of claim 7 , wherein the control node is one of the rectifier output or the second AC input.