IP Library Granted Patent US 9,384,786
Granted Patent B2
US 9,384,786 · App. 15/007,235 · Granted Jul 5, 2016

Power management in an electronic system through reducing energy usage of a battery and/or controlling an output power of an amplifier thereof

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Quick Facts
Patent No.
US 9,384,786
App. No.
15/007,235
Granted
Jul 5, 2016
Kind
B2
Abstract

A method includes automatically charging a capacitor coupled to a battery configured to power a memory through a charge switch that is closed whenever a voltage of the battery exceeds a recovery trip voltage or exceeds a shutdown trip voltage but is less than the recovery trip voltage and opened whenever the voltage of the battery drops below the shutdown trip voltage such that a minimum voltage of the shutdown trip voltage is maintained on the battery, thereby enabling the memory to retain information therein. The method also includes rendering a stored energy of the capacitor available to all circuitry coupled to the battery following the charging thereof through coupling the capacitor in parallel with the battery based on closure of a discharge switch following the charging of the capacitor.

Claims (13)

1. A method comprising:

automatically charging a capacitor coupled to a battery configured to power a memory through a charge switch that is closed whenever a voltage of the battery one of: exceeds a recovery trip voltage and exceeds a shutdown trip voltage but is less than the recovery trip voltage and opened whenever the voltage of the battery drops below the shutdown trip voltage such that a minimum voltage of the shutdown trip voltage is maintained on the battery, thereby enabling the memory to retain information therein; and

rendering a stored energy of the capacitor available to all circuitry coupled to the battery following the charging thereof through coupling the capacitor in parallel with the battery based on closure of a discharge switch following the charging of the capacitor.

2. The method of claim 1 , comprising opening and closing the charge switch and the discharge switch through a switch logic configured to have outputs of a high comparator and a low comparator as inputs thereto, the high comparator being configured to perform a comparison of the voltage of the battery and the recovery trip voltage, and the low comparator being configured to perform a comparison of the voltage of the battery and the shutdown trip voltage.

3. The method of claim 1 , further comprising charging the capacitor through a charging resistor coupled in series between the charge switch and the capacitor.

4. A system comprising:

a battery configured to power a memory;

a capacitor coupled to the battery through a charge switch and a discharge switch; and

a switch logic:

to enable automatic charging of the capacitor through closing the charge switch whenever a voltage of the battery one of: exceeds a recovery trip voltage and exceeds a shutdown trip voltage but is less than the recovery trip voltage and opening the charge switch whenever the voltage of the battery drops below the shutdown trip voltage such that a minimum voltage of the shutdown trip voltage is maintained on the battery, thereby enabling the memory to retain information therein, and

to render a stored energy of the capacitor available to all circuitry coupled to the battery following the charging thereof through coupling the capacitor in parallel with the battery based on closure of the discharge switch following the charging of the capacitor.

5. The system of claim 4 , further comprising: a high comparator and a low comparator configured to have outputs thereof as inputs to the switch logic, the high comparator being configured to perform a comparison of the voltage of the battery and the recovery trip voltage, and the low comparator being configured to perform a comparison of the voltage of the battery and the shutdown trip voltage.

6. The system of claim 4 , further comprising a charging resistor coupled in series between the charge switch and the capacitor to charge the capacitor.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2017
From: GIGPEAK, INC.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 043207/0576 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
CHANGE OF NAME Recorded Feb 21, 2017
From: GIGOPTIX, INC.
To: GIGPEAK, INC.
Reel/Frame 041304/0146 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2017
From: TAHOE RF SEMICONDUCTOR, INC.
To: GIGOPTIX, INC.
Reel/Frame 041282/0876 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2017
From: SCHILLER, CHRISTOPHER T.; SHAW, MICHAEL JOSEPH
To: TAHOE RF SEMICONDUCTOR, INC.
Reel/Frame 041232/0538 →