Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system
View Patent ↗A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.
1. A flag logic circuit for use in a multi-queue memory device having a plurality of queues, the flag logic circuit comprising:
a first stage storage element having a capacity to store a flag value for each of the queues in the multi-queue memory device;
a flag status bus having a capacity to provide N flag values;
a status bus control circuit configured to receive a signal that identifies a first number M of one or more queues used in the multi-queue memory device, and in response, generate a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1; and
a selector circuit coupled to receive the flag values stored in the first stage storage element and the repeating pattern of X control values, wherein the selector circuit is configured to route X sets of N flag values from the first stage storage element to the flag status bus in response to the repeating pattern of X control values.
2. The flag logic circuit of claim 1 , further comprising means for causing the status bus control circuit to provide a user defined pattern of control values in place of the repeating pattern of X control values.
3. A method of operating a flag status bus having a capacity to provide N flag values in a multi-queue memory device having a plurality of queues, the method comprising:
storing a flag value for each of the plurality of queues a first stage storage element;
identifying a first number M of one or more queues used in the multi-queue memory device;
generating a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1; and
sequentially routing X sets of N flag values from the first stage storage element to the flag status bus in response to the repeating pattern of X control values.