Crystal-less jitter attenuator

1. An integrated circuit to remove jitter from a clock signal, comprising:

an integrated circuit die, further comprising:

a signal comparator, the signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal, wherein the signal comparator is a frequency comparator that counts a first number of clock cycles occurring on the correction signal within a fixed time window, and the frequency comparator counts a second number of clock cycles occurring on the jittery input clock signal within the fixed window of time;

a digital low pass filter, the digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal;

a free running crystal-less oscillator, the free running crystal-less oscillator produces a reference signal; and

a fractional output divider, the fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter, the fractional output divider utilizes the filtered output signal to establish a value to divide a frequency of the reference signal by to obtain a clean output clock signal, the clean output clock signal is fed back to the signal comparator as the correction signal.

2. An integrated circuit to remove jitter from a clock signal, comprising:

an integrated circuit die, further comprising:

a signal comparator, the signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal;

a digital low pass filter, the digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal;

a free running crystal-less oscillator, the free running crystal-less oscillator produces a reference signal;

a fractional output divider, the fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter, the fractional output divider utilizes the filtered output signal to establish a value to divide a frequency of the reference signal by to obtain a clean output clock signal, the clean output clock signal is fed back to the signal comparator as the correction signal; and

wherein the signal comparator is a time to digital converter, the time to digital converter determines a phase difference between the jittery input clock signal and the correction signal, the digital low pass filter receives and filters the phase difference to provide the filtered output signal.

3. The integrated circuit of claim 2 , wherein the free running crystal-less oscillator is constructed with an LC oscillator, the LC oscillator is located on the integrated circuit die.

4. The integrated circuit of claim 2 , wherein the free running crystal-less oscillator is constructed with a ring oscillator, the ring oscillator is located on the integrated circuit die.

5. The integrated circuit of claim 2 , wherein a resonator of the free running crystal-less oscillator is selected from the group consisting of an LC resonator, a ring resonator, a bulk acoustic wave resonator, a surface acoustic wave resonator, and a micro-electromechanical system resonator.

6. The integrated circuit of claim 2 , where the clock signal is used in a communication channel which utilizes a protocol selected form the group consisting of Ethernet (IEEE 802.3 standard), Universal Serial Bus (USB,) High Definition Multimedia Interface (HDMI,) and IEEE 1394 standard.

7. An integrated circuit to remove jitter from a clock signal, comprising:

a signal comparator, the signal comparator is configured to average a jittery input clock signal, the signal comparator determines a physical difference between an average of the jittery input clock signal and a correction signal;

a digital low pass filter, the digital low pass filter is coupled to receive and filter the physical difference and to provide a filtered output signal;

a free running crystal-less oscillator, the free running crystal-less oscillator produces a reference signal;

a fractional output divider, the fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter, the fractional output divider utilizes the filtered output signal to establish a value to divide a frequency of the reference signal by to obtain a clean output clock signal, the clean output clock signal is fed back to the signal comparator as the correction signal;

a temperature sensor, the temperature sensor monitors a temperature of the free running crystal-less oscillator;

temperature compensation logic, an output of the temperature sensor and the temperature compensation logic are used to produce a correction factor; and

a summer, the summer adds the correction factor to the filtered output signal to produce a corrected input signal, the corrected input signal is input to the fractional output divider to remove an effect of the temperature on a desired frequency of the clean output clock signal.

8. The integrated circuit of claim 7 , wherein the integrated circuit is formed on an integrated circuit die and further wherein a resonator of the free running crystal-less oscillator is located off of the integrated circuit die.

9. A method to remove jitter from a clock signal, comprising:

determining a physical difference between a jittery input signal and a correction signal, wherein the physical difference is a phase difference obtained with a time to digital converter;

filtering the physical difference to produce a low pass filtered output signal;

dividing a frequency of a free running crystal-less oscillator reference signal with a fractional output divider to produce a clean output clock signal, wherein the fractional output divider uses the physical difference to select a value for the dividing;

establishing a frequency relationship between the jittery input clock signal and the clean output clock signal; and

feeding back the clean output clock signal to the determining wherein the clean output clock signal is used as the correction signal.

10. A method to remove jitter from a clock signal, comprising:

determining a physical difference between a jittery input signal and a correction signal;

filtering the physical difference to produce a low pass filtered output signal;

dividing a frequency of a free running crystal-less oscillator reference signal with a fractional output divider to produce a clean output clock signal, wherein the fractional output divider uses the physical difference to select a value for the dividing;

establishing a frequency relationship between the jittery input clock signal and the clean output clock signal;

feeding back the clean output clock signal to the determining wherein the clean output clock signal is used as the correction signal;

measuring a temperature of the free running crystal-less oscillator; and

using the temperature with temperature compensation logic to modify the filtered output signal so that an effect of the temperature on a desired frequency of the clean output clock signal is removed.

11. The method of claim 10 wherein the clock signal is used in a communications channel.

12. The method of claim 11 , wherein the communication channel utilizes a protocol selected form the group consisting of Ethernet (IEEE 802.3 standard), Universal Serial Bus (USB,) High Definition Multimedia Interface (HDMI,) and IEEE 1394 standard.