IP Library Granted Patent US 8,009,719
Granted Patent B2
US 8,009,719 · App. 11/904,895 · Granted Aug 30, 2011

Digital spread spectrum method based on precise phase delta-sigma algorithm

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Quick Facts
Patent No.
US 8,009,719
App. No.
11/904,895
Granted
Aug 30, 2011
Kind
B2
Abstract

A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals; quantizing a spread spectrum profile associated with the spread spectrum parameter; mapping the quantized profile; generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal; dividing a phase signal of the plurality of phase signals with the integer control signal; synchronizing the divided phase signal using the phase control signal; and providing a reference clock for a spread spectrum clock generator based on the synchronizing.

Claims (45)

1. A method comprising:

receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals;

quantizing a spread spectrum profile associated with the spread spectrum parameter;

mapping the quantized profile;

generating control signals based on the mapping, wherein the control signals include an integer control signal and a phase control signal;

dividing a phase signal of the plurality of phase signals with the integer control signal;

synchronizing the divided phase signal using the phase control signal; and

providing a reference clock for a spread spectrum clock generator based on the synchronizing.

2. The method of claim 1 , wherein synchronizing involves using a two stage synchronization circuit that receives the phase control signal and provides the reference clock based on the phase control signal and the divided phase signal.

3. The method of claim 2 , wherein generating the phase control signal includes generating a phase synchronization signal for selecting a phase signal of the plurality of phase signals to be a clock for the first stage of the synchronization circuit.

4. The method of claim 2 , wherein generating the phase control signal includes generating a phase select signal for selecting a phase signal of the plurality of phase signals to be a clock for the second stage of the synchronization circuit.

5. The method of claim 1 , wherein mapping the quantized profile comprises:

converting the quantized signal of the quantized spread spectrum profile into a signed quantized signal;

determining whether the signed quantized signal is larger than the number of levels of the multiple level parameter; and

converting the signed quantized signal to an integer period signal and a phase format signal based on the determination.

6. A system comprising:

a phase locked loop providing a spread spectrum parameter including a multiple-level parameter comprising a plurality of phase signals; and

a phase spread spectrum controller that receives the spread spectrum parameter, the phase spread spectrum controller comprising:

a phase mapper configured to map a quantized spread spectrum profile associated with the spread spectrum parameter,

a phase controller configured to generate control signals based on the map profile, wherein the control signals include an integer control signal and a phase control signal,

an integer divider configured to divide a phase signal of the plurality of phase signals with the integer control signal, and

a phase synchronizer configured to synchronize the divided phase signal using the phase control signal to generate a reference clock for a spread spectrum clock generator.

7. The system of claim 6 , wherein the phase synchronizer includes a synchronization circuit including a first register and a second register.

8. The system of claim 7 , wherein the phase controller generates the phase control signal including a phase synchronization signal for selecting a phase signal of the plurality of phase signals to be clocked into the first register of the synchronization circuit.

9. The system of claim 7 , wherein the phase controller generates the phase control signal including a phase select signal for selecting a phase signal of the plurality of phase signals to be clocked into the second register of the synchronization circuit.

10. The system of claim 6 , wherein the phase mapper comprises:

a two's complement converter configured to convert the quantized signal of the quantized spread spectrum profile into a signed quantized signal; and

a modul divider configured to determine whether the signed quantized signal is larger than the number of levels of the multiple level parameter and to convert the signed quantized signal to an integer period signal and a phase format signal based on the determination.

11. The system of claim 6 , wherein the phase spread spectrum controller further comprises:

a spread profile generator configured to receive the spread spectrum parameter from the phase locked loop and generate a spread spectrum profile; and

a Δ/Σ modulator for creating the quantized spread spectrum profile based on the spread spectrum profile.

12. An apparatus comprising:

a phase mapper configured to map a quantized spread spectrum profile associated with a spread spectrum parameter from a phase locked loop, wherein the spread spectrum parameter includes a multiple-level parameter comprising a plurality of phase signals;

a phase controller configured to generate control signals based on the map profile, wherein the control signals include an integer control signal and a control signal;

an integer divider configured to divide a phase signal of the plurality of phase signals with the integer control signal; and

a phase synchronizer configured to synchronize the divided phase signal using the phase control signal to generate a reference clock for a spread spectrum clock generator.

13. The apparatus of claim 12 , wherein the phase synchronizer includes a synchronization circuit comprising a first register and a second register.

14. The apparatus of claim 13 , wherein the phase controller generates the phase control signal including a phase synchronization signal for selecting a phase signal of the plurality of phase signals to be clocked into the first register of the synchronization circuit.

15. The apparatus of claim 13 , wherein the phase controller generates the phase control signal including a phase select signal for selecting a phase signal of the plurality of phase signals to be clocked into the second register of the synchronization circuit.

16. The apparatus of claim 12 , wherein the phase mapper comprises:

a two's complement converter configured to convert the quantized signal of the quantized spread spectrum profile into a signed quantized signal; and

a modul divider configured to determine whether the signed quantized signal is larger than the number of levels of the multiple-level parameter and to convert the signed quantized signal to an integer period signal and a phase format signal based on the determination.

17. The apparatus of claim 12 , further comprising:

a spread profile generator configured to receive the spread spectrum parameter from the phase locked loop and generate a spread spectrum profile; and

a Δ/Σ modulator for creating the quantized spread spectrum profile based on the spread spectrum profile.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →