Integrated circuits having low power, low interference and programmable delay generators therein and methods of operating same

1. A programmable delay generator, comprising:

a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit during a calibration operation; and

a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit upon conclusion of the calibration operation when said DCO is powered-down into an inactive state.

2. The programmable delay generator of claim 1 , wherein said calibration circuit comprises a current steering digital-to-analog converter (CSDAC) responsive to a digital calibration code and a current-to-voltage converter responsive to at least one current signal generated by said CSDAC; and wherein the current-to-voltage converter is active during the calibration operation and upon conclusion of the calibration operation when said DCO is powered-down into the inactive state.

3. The programmable delay generator of claim 2 , wherein the current-to-voltage converter is responsive to a pair of current signals generated by said CSDAC, which remains active when said DCO is powered-down into the inactive state; wherein a magnitude of the pair of analog current signals remains constant during calibration of said DCO; and wherein the first and second control signals are equivalent.

4. The programmable delay generator of claim 1 , wherein said DCO is configured as a ring oscillator.

5. The programmable delay generator of claim 1 , wherein said DCO is configured as a ring oscillator having N delay stages therein; and wherein said delay line has M stages therein, where N and M are positive integers and M is greater than N.

6. The programmable delay generator of claim 1 , wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO during the calibration operation; and wherein the periodic signal is disabled upon conclusion of the calibration operation.

7. The programmable delay generator of claim 1 , wherein said calibration circuit comprises a non-monotonic digital-to-analog converter (DAC).

8. A programmable delay generator, comprising:

a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit; and

a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit;

wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO; and

wherein the frequency comparator is configured to generate a varying multi-bit digital calibration code during a calibration operation and store a final digital calibration code upon completion of the calibration operation.

9. A programmable delay generator, comprising:

a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit; and

a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit;

wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO; and

wherein said calibration circuit comprises a feedback divider configured to generate the periodic feedback signal in response to the periodic signal generated by said DCO during a calibration operation; and wherein said DCO and the feedback divider are disabled into a low power state upon completion of the calibration operation.

10. A programmable delay generator, comprising:

a calibration circuit comprising a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein, said DCO having a frequency set by a first control signal generated by said calibration circuit; and

a delay line having a second plurality of delay stages therein that are replicas of the first plurality of delay stages within said DCO and responsive to a second control signal generated by said calibration circuit;

wherein said calibration circuit comprises a current steering digital-to-analog converter (CSDAC) responsive a digital calibration code and a current-to-voltage converter responsive to at least one current signal generated by said CSDAC; and

wherein said calibration circuit further comprises a frequency comparator responsive to a reference clock and a periodic feedback signal, which is synchronized to a periodic signal generated by said DCO, said frequency comparator configured to generate the digital calibration code as a varying code during a calibration operation and store a final digital calibration code upon completion of the calibration operation.

11. The programmable delay generator of claim 10 , wherein frequency comparison operations within said frequency comparator are terminated and said DCO is disabled into a low power state upon completion of the calibration operation.

12. A programmable delay generator, comprising:

a calibration circuit comprising a digitally-controlled oscillator (DCO) having a frequency set by a first control signal generated by said calibration circuit during a calibration operation when said DCO is active; and

a delay line having a plurality of delay stages therein that are responsive to a second control signal generated by said calibration circuit upon completion of the calibration operation when said DCO is inactive.

13. The programmable delay generator of claim 12 , wherein said DCO comprises a plurality of delay stages therein that are replicas of the plurality of delay stages in said delay line.

14. The programmable delay generator of claim 13 , wherein said DCO is configured as a ring oscillator; and wherein said calibration circuit comprises a feedback divider responsive a periodic signal generated by the ring oscillator.

15. The programmable delay generator of claim 14 , wherein said calibration circuit comprises a frequency comparator responsive to a reference clock and a periodic feedback signal generated by the feedback divider; and wherein the frequency comparator and feedback divider are disabled into respective low power states upon completion of the calibration operation.

16. The programmable delay generator of claim 15 , wherein said calibration circuit comprises a current steering digital-to-analog converter (CSDAC) responsive a digital calibration code generated by the frequency comparator; and wherein the CSDAC remains active during the calibration operation and post completion of the calibration operation.

17. The programmable delay generator of claim 16 , wherein a magnitude of a current generated by the CSDAC controls a frequency of the periodic signal generated by the ring oscillator during the calibration operation and controls a delay provided by the plurality of delay stages within the delay line post completion of the calibration operation.