Fast-response hybrid lock detector
The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.
1. An apparatus comprising:
an analog circuit configured to generate an enable signal in response to (i) a first comparison of a width of an up pulse and a pre-determined width and (ii) a second comparison of a width of a down pulse and said pre-determined width, wherein (a) said up pulse and said down pulse are generated in response to a comparison of a feedback signal and a reference signal and (b) said enable signal is active when both said first comparison and said second comparison are within a pre-determined threshold; and
a digital circuit configured to generate an output signal representing a lock status between (i) said feedback signal and (ii) said reference signal, wherein (A) said lock status is determined (a) during a decision window based on a number of pulses of said reference signal and (b) when said enable signal is active, and (B) said decision window is repeated periodically until said enable signal is not active.
2. The apparatus according to claim 1 , wherein said decision window starts after said enable signal is active.
3. The apparatus according to claim 1 , wherein said pre-determined threshold comprises a determination of a consecutive number of logical values corresponding to said width of said up pulse and said width of said down pulse.
4. The apparatus according to claim 3 , wherein (i) said logical values corresponding to said width of said up pulse are determined based on a filtering of said up pulse and (ii) said logical values corresponding to said width of said down pulse are determined based on a filtering of said down pulse.
5. The apparatus according to claim 1 , wherein said analog circuit implements a phase comparator.
6. The apparatus according to claim 5 , wherein said phase comparator comprises a shift sampling register.
7. The apparatus according to claim 6 , wherein said shift sampling register is implemented to remove meta-stability.
8. The apparatus according to claim 6 , wherein said shift sampling register is implemented to determine a consecutive number of logical values.
9. The apparatus according to claim 6 , wherein (i) said shift sampling register implements a 24-bit shift sampling register, (ii) a first eight stages of said 24-bit shift sampling register removes meta-stability and (iii) a last sixteen stages of said 24-bit shift sampling register determines whether there have been sixteen consecutive logical zero values.
10. The apparatus according to claim 6 , wherein said shift sampling register comprises a plurality of flip-flop circuits configured in series.
11. The apparatus according to claim 5 , wherein said phase comparator comprises a pulse sampling circuit configured to filter at least one of (a) said up pulse and (b) said down pulse.
12. The apparatus according to claim 1 , wherein said digital circuit implements a lock detector.
13. The apparatus according to claim 1 , wherein said decision window comprises 144 clock cycles.
14. The apparatus according to claim 1 , wherein said pre-determined width corresponds to 400 ps.
15. The apparatus according to claim 1 , wherein said apparatus is implemented in a memory.
16. The apparatus according to claim 1 , wherein said apparatus comprises a fast-response hybrid lock detector in a phase-locked loop.
17. The apparatus according to claim 1 , wherein (i) said up pulse is generated when said feedback signal is lower than said reference signal and (ii) said down pulse is generated when said feedback signal is higher than said reference signal.
18. An apparatus comprising:
an analog circuit configured to generate an enable signal in response to (i) a first comparison of a width of an up pulse and a pre-determined width and (ii) a second comparison of a width of a down pulse and said pre-determined width, wherein (a) said up pulse and said down pulse are generated in response to a comparison of a feedback signal and a reference signal and (b) said enable signal is active when both said first comparison and said second comparison are within a pre-determined threshold; and
a digital circuit configured to generate an output signal representing a lock status between (i) said feedback signal and (ii) said reference signal, wherein (A) said lock status is determined (a) during a decision window based on a number of pulses of said reference signal and (b) when said enable signal is active and (B) said output signal is presented to logic gates configured to disable said analog circuit when said output signal is active.
19. An apparatus comprising:
an analog circuit configured to generate an enable signal in response to (i) a first comparison of a width of an up pulse and a pre-determined width and (ii) a second comparison of a width of a down pulse and said pre-determined width, wherein (a) said up pulse and said down pulse are generated in response to a comparison of a feedback signal and a reference signal and (b) said enable signal is active when both said first comparison and said second comparison are within a pre-determined threshold; and
a digital circuit configured to generate an output signal representing a lock status between (i) said feedback signal and (ii) said reference signal, wherein (A) said lock status is determined (a) during a decision window based on a number of pulses of said reference signal and (b) when said enable signal is active and (B) said analog circuit is configured to enable said digital circuit to skip counting clock cycles when said feedback signal and said reference signal are far from final locking.