Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation
View Patent ↗FIFO memory devices are configured to support a pair of hybrid operating modes that enable the FIFO memory device to be depth-expandable with other FIFO memory devices in a collective standard mode of operation. The pair of hybrid operating modes including a first hybrid mode that supports a write interface configured in standard mode and a read interface configured in first-word fall-through (FWFT) mode and a second hybrid mode that supports a write interface configured in FWFT mode and a read interface configured in standard mode.
1. An integrated circuit device, comprising:
a first-in first-out (FIFO) memory chip configured to support a pair of hybrid operating modes that enable the FIFO memory chip to be depth-expandable with other FIFO memory chips in a collective standard mode of operation, said pair of hybrid operating modes including a first hybrid mode that supports a write interface configured in standard mode and a read interface configured in first-word fall-through (FWFT) mode and a second hybrid mode that supports a write interface configured in FWFT mode and a read interface configured in standard mode.
2. The device of claim 1 , wherein the first hybrid mode supports a write interface having a full flag pin that designates when said FIFO memory chip is full and a read interface having an output ready pin that designates when said FIFO memory chip has at least one entry therein.
3. The device of claim 2 , wherein the second hybrid mode supports a write interface having an input ready pin that designates when said FIFO memory chip can accept additional entries and a read interface having an empty flag pin that designates when said FIFO memory chip is empty.
4. The device of claim 3 , wherein said FIFO memory chip has a pin that is responsive to a standard depth expansion mode signal.
5. The device of claim 1 , wherein said FIFO memory chip comprises a FIFO memory controller chip having cache memory arrays therein and a external memory interface that supports read and write data transfers between the cache memory arrays and a random access memory device.
6. The device of claim 1 , wherein said FIFO memory chip comprises:
a first cache memory device having a first page of quad-port memory cells therein that is configured to support writing and reading of FIFO vectors to and from columns in the first page and writing and reading of memory vectors to and from rows in the first page.
7. An integrated circuit system, comprising:
a plurality of first-in first-out (FIFO) memory controller chips that collectively support standard mode operation when cascaded in a depth expansion configuration, said plurality of FIFO memory controller chips comprising:
a front-end FIFO memory controller chip disposed in a first hybrid mode that supports a corresponding write interface configured in standard mode and a corresponding read interface configured in first-word fall-through (FWFT) mode; and
a back-end FIFO memory controller chip disposed in a second hybrid mode that supports a corresponding write interface configured in FWFT mode and a corresponding read interface configured in standard mode.
8. An integrated circuit device, comprising:
a first-in first-out (FIFO) memory chip having cache and embedded memory elements therein, said FIFO memory chip configured to support a pair of hybrid operating modes that enable said FIFO memory chip to be depth-expandable with other FIFO memory chips in a collective standard mode of operation, said pair of hybrid operating modes including a first hybrid mode that supports a write interface configured in standard mode and a read interface configured in first-word fall-through (FWFT) mode and a second hybrid mode that supports a write interface configured in FWFT mode and a read interface configured in standard mode.
9. The device of claim 8 , wherein the first hybrid mode supports a write interface having a full flag pin that designates when said FIFO memory chip is full and a read interface having an output ready pin that designates when said FIFO memory chip has at least one entry therein.
10. The device of claim 9 , wherein the second hybrid mode supports a write interface having an input ready pin that designates when said FIFO memory chip can accept additional entries and a read interface having an empty flag pin that designates when said FIFO memory chip is empty.
11. The device of claim 10 , wherein said FIFO memory chip has a pin that is responsive to a standard depth expansion mode signal.
12. An integrated circuit device, comprising:
a first-in first-out (FIFO) memory chip configured to support at least one hybrid operating mode that enables said FIFO memory chip to be depth-expandable with another FIFO memory chip in a collective standard mode of operation, said at least one hybrid mode supporting a write interface configured in standard mode and a read interface configured in first-word fall-through (FWFT) mode.