Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein
View Patent ↗Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) according to delay. Each of the plurality of delay chain units may include a respective phase comparator. Each phase comparator is configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal applied to an input of the delay chain. This fraction of a period may be equivalent to one-half or other percentage of a period of the reference clock signal. The phase comparators with the delay chain units operate to generate a multi-bit delay value signal, which is provided to a delay chain control circuit.
1. A locked loop integrated circuit, comprising:
a delay chain having a plurality of delay chain units therein that respectively comprise a phase comparator configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal applied to an input of the delay chain.
2. The circuit of claim 1 , wherein each of the plurality of delay chain units is configured to support a respective delay path and a respective bypass path therein.
3. The circuit of claim 2 , wherein the delay chain is responsive to a multi-bit delay unit enable signal having a value that identifies which ones of the delay paths are active within the plurality of delay chain units.
4. The circuit of claim 1 , wherein each of the plurality of delay chain units comprises a respective inverter delay line; and wherein the phase comparator in each of the plurality of delay chain units has inputs that tap off at least two nodes of a corresponding inverter delay line.
5. The circuit of claim 1 , wherein said delay chain is configured to generate a multi-bit delay value signal that identifies which ones of the plurality of delay chain units are configured to provide a delay in excess of one-half the period of the reference clock signal.
6. The circuit of claim 1 , wherein said delay chain is configured to generate a multi-bit delay value signal that identifies which ones of the plurality of delay chain units are configured to provide said delay in excess of the fraction of the period of the reference clock signal.
7. The circuit of claim 6 , further comprising a delay chain control circuit having a system clock generator therein, said system clock generator comprising a plurality of clock dividers, which are responsive to the reference clock signal, and a clock selector configured to select an output of one of the plurality of clock dividers as a system clock, in response to the multi-bit delay value signal.
8. The circuit of claim 1 , further comprising a delay chain control circuit having a system clock generator therein, said system clock generator comprising a plurality of clock dividers, which are responsive to the reference clock signal, and a clock selector configured to select an output of one of the plurality of clock dividers as a system clock, in response to a multi-bit delay value signal generated by said delay chain.
9. The circuit of claim 5 , further comprising:
a phase comparator configured to generate a lock signal and a compare signal in response to the reference clock signal and a feedback clock signal derived from an output of said delay chain; and
a delay chain control circuit responsive to the lock and compare signals and having a system clock generator therein, said system clock generator comprising a plurality of clock dividers, which are responsive to the reference clock signal, and a clock selector configured to select an output of one of the plurality of clock dividers as a system clock, in response to the multi-bit delay value signal.
10. The circuit of claim 9 , wherein said delay chain control circuit is further configured to generate a multi-bit delay unit enable signal; and wherein said delay chain is responsive to the multi-bit delay unit enable signal.
11. The circuit of claim 10 , wherein said delay chain control circuit is configured so that a maximum rate of change of the multi-bit delay unit enable signal increases as a frequency of the system clock increases.
12. An integrated circuit delay chain, comprising:
a plurality of delay chain units having respective phase comparators therein that are configured to identify whether a delay provided by the corresponding delay chain unit exceeds a fraction of a period of a reference clock signal received at an input of a first one of the plurality of delay chain units in the delay chain.
13. The delay chain of claim 12 , wherein each of the plurality of delay chain units comprises a respective inverter delay line; and wherein the phase comparator in each of the plurality of delay chain units has inputs that tap off at least two nodes of a corresponding inverter delay line.