Automatic gain control with programmable attack and decay times
View Patent ↗A transconductance comparator includes a comparator having an output of a detector configured to sense an amplitude of an output of a Variable Gain Amplifier (VGA) of a receiver as a first input and a reference amplitude level as a second input. The comparator generates an error signal based on the first input and the second input. The transconductance comparator also includes a transconductance amplifier having a differential voltage input based on the error signal generated through the comparator and generating an output current. The transconductance amplifier includes current sources associated with programmable current limits thereof and differential pairs associated with the current sources, one or more of which is implemented with a size mismatch between transistors thereof to eliminate an offset error due to a mismatch between the current limits, thereby enabling programmability of an attack time and a decay time during automatic gain control of the VGA.
1. A transconductance comparator comprising:
a comparator having an output of a detector configured to sense an amplitude of an output of a Variable Gain Amplifier (VGA) of a receiver as a first input and a reference amplitude level as a second input thereto, the comparator being configured to generate an error signal based on the first input and the second input; and
a transconductance amplifier configured to have a differential voltage input based on the error signal generated through the comparator and to generate an output current, the transconductance amplifier comprising:
a first current source associated with a programmable lower current limit of the transconductance amplifier;
a second current source associated with a programmable upper current limit of the transconductance amplifier;
a first differential pair coupled to the first current source and configured to have a first voltage of the differential voltage input applied to gate terminals of transistors thereof; and
a second differential pair coupled to the second current source and configured to have a second voltage of the differential voltage input applied to gate terminals of transistors thereof,
wherein at least one of: the transistors of the first differential pair and the transistors of the second differential pair are implemented with a size mismatch therebetween to eliminate an offset error in the transconductance amplifier due to a mismatch between the programmable lower current limit and the programmable upper current limit, the elimination of the offset error enabling programmability of an attack time and a decay time during automatic gain control of the VGA over a wide range of the programmable current limits of the transconductance amplifier.
2. The transconductance comparator of claim 1 ,
wherein the first differential pair of the transconductance amplifier is implemented with at least one of n-channel Metal-Oxide-Semiconductor (MOS) transistors and NPN bipolar transistors, and
wherein the second differential pair of the transconductance amplifier is implemented with at least one of p-channel MOS transistors and PNP bipolar transistors.
3. The transconductance comparator of claim 2 ,
wherein drain terminals of a transistor of the first differential pair and a transistor of the second differential pair are coupled to each other,
wherein source terminals of the transistors of the first differential pair are coupled to each other,
wherein source terminals of the transistors of the second differential pair are also coupled to each other,
wherein a drain terminal of another transistor of the first differential pair and bulk terminals of the transistors of the second differential pair are held at a supply voltage of each of the first current source and the second current source,
wherein a drain terminal of another transistor of the second differential pair is held at a ground potential, and
wherein bulk terminals of the transistors of the first differential pair are coupled to substrate terminals thereof.
4. The transconductance comparator of claim 3 ,
wherein an output terminal of the transconductance amplifier is taken from a path coupling the drain terminals of the transistor of the first differential pair and the transistor of the second differential pair.
5. The transconductance comparator of claim 3 ,
wherein at least one of the transistor of the first differential pair and the transistor of the second differential pair whose drain terminals are coupled to each other is at least 10 times smaller than the corresponding at least of the another transistor of the first differential pair and the another transistor of the second differential pair whose drain terminals are held at the supply voltage and the ground potential respectively.
6. The transconductance comparator of claim 1 , wherein the current limits of the transconductance amplifier are programmable based on one of: a varying reference voltage and a varying bias current.
7. An automatic gain control circuit of a VGA comprising:
a detector to sense an amplitude of an output of the VGA;
a comparator having an output of the detector as a first input and a reference amplitude level as a second input thereto, the comparator being configured to generate an error signal based on the first input and the second input;
a transconductance amplifier configured to have a differential voltage input based on the error signal generated through the comparator and to generate an output current, an output of the transconductance amplifier being configured to be applied to the VGA to effect an automatic gain control, and the transconductance amplifier comprising:
a first current source associated with a programmable lower current limit of the transconductance amplifier;
a second current source associated with a programmable upper current limit of the transconductance amplifier;
a first differential pair coupled to the first current source and configured to have a first voltage of the differential voltage input applied to gate terminals of transistors thereof; and
a second differential pair coupled to the second current source and configured to have a second voltage of the differential voltage input applied to gate terminals of transistors thereof, at least one of: the transistors of the first differential pair and the transistors of the second differential pair being implemented with a size mismatch therebetween to eliminate an offset error in the transconductance amplifier due to a mismatch between the programmable lower current limit and the programmable upper current limit, and the elimination of the offset error enabling programmability of an attack time and a decay time during the automatic gain control of the VGA over a wide range of the programmable current limits of the transconductance amplifier; and
a capacitor coupled between the output of the transconductance amplifier and a ground terminal, the capacitor being configured to be charged and discharged by the transconductance amplifier.
8. The automatic gain control circuit of claim 7 ,
wherein the first differential pair of the transconductance amplifier is implemented with at least one of n-channel MOS transistors and NPN bipolar transistors, and
wherein the second differential pair of the transconductance amplifier is implemented with at least one of p-channel MOS transistors and PNP bipolar transistors.
9. The automatic gain control circuit of claim 8 ,
wherein drain terminals of a transistor of the first differential pair of the transconductance amplifier and a transistor of the second differential pair of the transconductance amplifier are coupled to each other,
wherein source terminals of the transistors of the first differential pair of the transconductance amplifier are coupled to each other,
wherein source terminals of the transistors of the second differential pair of the transconductance amplifier are also coupled to each other,
wherein a drain terminal of another transistor of the first differential pair of the transconductance amplifier and bulk terminals of the transistors of the second differential pair of the transconductance amplifier are held at a supply voltage of each of the first current source and the second current source thereof,
wherein a drain terminal of another transistor of the second differential pair of the transconductance amplifier is held at a ground potential, and
wherein bulk terminals of the transistors of the first differential pair of the transconductance amplifier are coupled to substrate terminals thereof.
10. The automatic gain control circuit of claim 9 ,
wherein an output terminal of the transconductance amplifier is taken from a path coupling the drain terminals of the transistor of the first differential pair and the transistor of the second differential pair thereof.
11. The automatic gain control circuit of claim 9 ,
wherein at least one of the transistor of the first differential pair of the transconductance amplifier and the transistor of the second differential pair of the transconductance amplifier whose drain terminals are coupled to each other is at least 10 times smaller than the corresponding at least one of the another transistor of the first differential pair of the transconductance amplifier and the another transistor of the second differential pair of the transconductance amplifier whose drain terminals are held at the supply voltage and the ground potential respectively.
12. A Radio Frequency (RF) receiver comprising:
a mixer;
a VGA to amplify an output of the mixer; and
an automatic gain control circuit to control a gain of the VGA, the automatic gain control circuit comprising:
a detector to sense an amplitude of an output of the VGA;
a comparator having an output of the detector as a first input and a reference amplitude level as a second input thereto, the comparator being configured to generate an error signal based on the first input and the second input;
a transconductance amplifier configured to have a differential voltage input based on the error signal generated through the comparator and to generate an output current, an output of the transconductance amplifier being configured to be applied to the VGA to effect an automatic gain control, and the transconductance amplifier comprising:
a first current source associated with a programmable lower current limit of the transconductance amplifier;
a second current source associated with a programmable upper current limit of the transconductance amplifier;
a first differential pair coupled to the first current source and configured to have a first voltage of the differential voltage input applied to gate terminals of transistors thereof; and
a second differential pair coupled to the second current source and configured to have a second voltage of the differential voltage input applied to gate terminals of transistors thereof, at least one of: the transistors of the first differential pair and the transistors of the second differential pair being implemented with a size mismatch therebetween to eliminate an offset error in the transconductance amplifier due to a mismatch between the programmable lower current limit and the programmable upper current limit, and the elimination of the offset error enabling programmability of an attack time and a decay time during the automatic gain control of the VGA over a wide range of the programmable current limits of the transconductance amplifier; and
a capacitor coupled between the output of the transconductance amplifier and a ground terminal, the capacitor being configured to be charged and discharged by the transconductance amplifier.
13. The RF receiver of claim 12 , wherein the mixer is an Intermediate Frequency (IF) mixer.
14. The RF receiver of claim 13 , further comprising:
a RF mixer to mix an RF input with a local oscillator (LO) signal; and
another VGA to amplify an output of the RF mixer,
wherein the automatic gain control circuit is also configured to control a gain of the another VGA.
15. The RF receiver of claim 12 , wherein the RF receiver is one of an anti-jamming receiver, a consumer system receiver and a satellite communication receiver.
16. The RF receiver of claim 14 , wherein the automatic gain control circuit to configured to control the gain of the VGA at a same level as the gain of the another VGA.
17. The RF receiver of claim 12 ,
wherein the first differential pair of the transconductance amplifier is implemented with at least one of n-channel MOS transistors and NPN bipolar transistors, and
wherein the second differential pair of the transconductance amplifier is implemented with at least one of p-channel MOS transistors and PNP bipolar transistors.
18. The RF receiver of claim 17 ,
wherein drain terminals of a transistor of the first differential pair of the transconductance amplifier and a transistor of the second differential pair of the transconductance amplifier are coupled to each other,
wherein source terminals of the transistors of the first differential pair of the transconductance amplifier are coupled to each other,
wherein source terminals of the transistors of the second differential pair of the transconductance amplifier are also coupled to each other,
wherein a drain terminal of another transistor of the first differential pair of the transconductance amplifier and bulk terminals of the transistors of the second differential pair of the transconductance amplifier are held at a supply voltage of each of the first current source and the second current source thereof,
wherein a drain terminal of another transistor of the second differential pair of the transconductance amplifier is held at a ground potential, and
wherein bulk terminals of the transistors of the first differential pair of the transconductance amplifier are coupled to substrate terminals thereof.
19. The RF receiver of claim 18 ,
wherein an output terminal of the transconductance amplifier is taken from a path coupling the drain terminals of the transistor of the first differential pair and the transistor of the second differential pair thereof.
20. The RF receiver of claim 18 ,
wherein at least one of the transistor of the first differential pair of the transconductance amplifier and the transistor of the second differential pair of the transconductance amplifier whose drain terminals are coupled to each other is at least 10 times smaller than the corresponding at least one of the another transistor of the first differential pair of the transconductance amplifier and the another transistor of the second differential pair of the transconductance amplifier whose drain terminals are held at the supply voltage and the ground potential respectively.