IP Library Granted Patent US 7,268,599
Granted Patent B1
US 7,268,599 · App. 11/050,009 · Granted Sep 11, 2007

Method and apparatus for buffer with programmable skew

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Quick Facts
Patent No.
US 7,268,599
App. No.
11/050,009
Granted
Sep 11, 2007
Kind
B1
Abstract

A method and apparatus for a buffer with programmable skew have been disclosed. Several output signals are generated. Based on one of the output signals several feedback signals are generated. The feedback signals are then received and compared. Based on the comparisons, the skew between the output signals is adjusted.

Claims (16)

1. A method comprising:

generating a first output;

generating a first feedback output based on said first output;

generating a second feedback output based on said first output;

generating a second output, wherein said first output and said second output are generated from a same signal;

receiving a first feedback input signal related to said first feedback output, wherein said received first feedback input signal is received at a phase lock loop and at a phase detector;

receiving a second feedback input signal related to said second feedback output, wherein said received second input feedback signal is received at said phase detector; and

adjusting a skew between said first output and said second output, wherein adjusting said skew further comprises delaying said second output.

2. The method of claim 1 wherein said delaying further comprises:

comparing a phase of said received first feedback signal and said received second feedback signal and outputting a phase comparison signal;

looking up a value based on said phase comparison signal; and

adjusting a delay of said second output based on said lookup value.

3. The method of claim 2 wherein said phase lock loop is a single phase lock loop.

4. The method of claim 2 wherein said adjusting said delay is further based on said same signal.

5. The method of claim 2 wherein said adjusting said delay is not based on said same signal.

6. The method of claim 2 wherein said adjusting said delay is further based on a second signal from said phase lock loop.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY INTEREST Recorded Jul 25, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 043095/0414 →