Reconfigurable divider circuits with hybrid structure

1. An integrated circuit comprising:

a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal;

a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal; and

a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.

2. An integrated circuit comprising:

a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal;

a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal, wherein the second variable divider circuit comprises:

a plurality of groups of cascade-connected flip-flops having clock inputs that receive the clock signal;

a plurality of first multiplexer circuits, respective ones of which have inputs coupled to outputs of flip-flops of respective ones of the groups of flip-flops and configured to selectively pass signals therefrom to a data input of another one of the groups of flip-flops;

a second multiplexer circuit coupled to an output of a last one of the groups of flip-flops and configured to selectively pass signals therefrom to output the second divided clock signal; and

a feedback circuit having an input coupled to the second multiplexer circuit and an output coupled to a first one of the groups of flip-flops; and

a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.

3. The integrated circuit of claim 2 , wherein the groups of flip-flops have different numbers of flip-flops and wherein the first and second multiplexer circuits are controllable to provide variable length flip-flop chains.

4. The integrated circuit of claim 3 , wherein, for each group of flip-flops, a first multiplexer circuit is configured to bypass no flip-flops of the group in a first state and to bypass all but one flip-flop of the group in a second state.

5. The integrated circuit of claim 3 , wherein the groups of flip-flops and the first and second multiplexer circuits are arranged such that the flip-flop chains do not include any more than one multiplexer circuit between any two consecutive flip-flops.

6. The integrated circuit of claim 2 , wherein the feedback circuit is configured to support even and odd integer division.

7. The integrated circuit of claim 6 , wherein the feedback circuit comprises:

first and second cascade connected flip-flops, an input of the first flip-flop coupled to an output of the second multiplexer circuit;

a third multiplexer circuit having a first input coupled to an output of the first multiplexer circuit and a second input coupled to a logic level node; and

a NAND circuit having a first input coupled to an output of the third multiplexer circuit, a second input coupled to an output of the second flip-flop and an output coupled to an input of the first one of the groups of flip-flops.

8. The integrated circuit of claim 2 , wherein the first variable divider circuit comprises:

a chain of cascade-connected flip-flops; and

a multiplexer circuit configured to selectively couple outputs of the flip-flops of the chain to an input of the chain.

9. The integrated circuit of claim 1 , further comprising at least one duty cycle correction circuit coupled to outputs of the first and second variable divider circuits.

10. An integrated circuit comprising:

a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal;

a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal; and

a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input, wherein the second variable divider circuit provides less inter-flip-flop delay than the first variable divider circuit.

11. The integrated circuit of claim 1 , wherein at least one of the first and second variable divider circuits comprises:

a plurality of groups of cascade-connected flip-flops having clock inputs that receive the clock signal;

a plurality of first multiplexer circuits, respective ones of which are coupled to outputs of flip-flops of respective ones of the groups of cascaded flip-flops and configured to selectively pass signals therefrom to a data input of another one of the groups of flip-flops;

a second multiplexer circuit coupled to a last one of the groups of flip-flops and configured to selectively pass signals therefrom to output a divided clock signal; and

a feedback circuit having an input coupled to the second multiplexer circuit and an output coupled to a first one of the groups of flip-flops.

12. The integrated circuit of claim 11 , wherein the groups of flip-flops have different numbers of flip-flops and wherein the first and second multiplexer circuits are controllable to provide variable length flip-flop chains.

13. The integrated circuit of claim 12 , wherein, for each group of flip-flops, a first multiplexer circuit is configured to bypass no flip-flops of the group in a first state and to bypass all but one flip-flop of the group in a second state.

14. The integrated circuit of claim 12 , wherein the groups of flip-flops and the first and second multiplexer circuits are arranged such that the flip-flop chains do not include any more than one multiplexer circuit between any two consecutive flip-flops.

15. The integrated circuit of claim 11 , wherein the feedback circuit is configured to support even and odd integer division.

16. The integrated circuit of claim 15 , wherein the feedback circuit comprises:

first and second cascade connected flip-flops, an input of the first flip-flop coupled to an output of the second multiplexer circuit;

a third multiplexer circuit having a first input coupled to an output of the first multiplexer circuit and a second input coupled to a fixed logic level node; and

a NAND circuit having a first input coupled to an output of the third multiplexer circuit, a second input coupled to an output of the second flip-flop and an output coupled to an input of a first one of the groups of flip-flops.

17. The integrated circuit of claim 1 :

wherein the first variable divider circuit comprises a series of cascade-connected flip-flops having clock inputs that receive a clock signal and a first multiplexer circuit configured to selectively couple outputs of the flip-flops of the series to an input of the series of flip-flops to generate the first divided clock signal at an output of the series of flip-flops; and

wherein the second variable divider circuit comprises a plurality of groups of cascade-connected flip-flops having clock inputs that receive the clock signal, a plurality of second multiplexer circuits, respective ones of which are coupled to outputs of flip-flops of respective ones of the groups of cascaded flip-flops and configured to selectively pass signals therefrom to a data input of another one of the groups of flip-flops, a third multiplexer circuit coupled to an outputs of a last one of the groups of flip-flops and configured to selectively pass signals therefrom to produce the second divided clock signal and a feedback circuit having an input coupled to the third multiplexer and an output coupled to a first one of the group of flip-flops.

18. The integrated circuit of claim 17 , wherein the first variable divider circuit provides a lower range of division factors and wherein the second variable divider circuit provides an upper range of division factors.

19. The integrated circuit of claim 17 , wherein the second variable divider circuit provides less inter-flip-flop delay than the first variable divider circuit.