Overclocking with phase selection
View Patent ↗A novel solution that combines the technologies of fractional divider and phase selection is provided to implement over-clocking for CPU PLL in PC clock generator with a set resolution that is independent of the clock frequency.
1. A timing circuit comprising:
a CPU phase-locked loop (PLL) which provides a CPU clock signal with an overclocking step resolution that is not a multiple of the CPU output frequency and is implemented in circuitry according to the following equation:
((N actual *ref_clk)/P)/N
where N actual is an actual CPU frequency output by the CPU PLL, ref_clk is a reference clock received by the CPU PLL, P is a dividing value used by a P-divider, and N is a dividing value used by a fractional N-divider; and
a phase selection circuit that provides control signals to the fractional N-divider in response to input signals;
wherein the fractional N-divider is coupled to receive the VCO clock signal and provides a feedback clock;
wherein the P-divider provides the CPU clock signal based on the VCO clock signal;
wherein the CPU PLL receives the reference clock and the feedback clock and outputs a VCO clock signal in response to a comparison between the reference clock and the feedback clock; and
wherein the value P of the P-divider and the input signals to the phase selection circuit are chosen so that the step resolution is fixed while the VCO clock signal has a frequency less than a set frequency.
2. The circuit in claim 1 , wherein the control signals include a dividing value signal (Ndiv[8:0]) and a phase selection signal (phase_sel[3:0]).
3. The circuit in claim 2 , wherein the VCO clock signal includes three differently-phased clock signals equally separated in phase.
4. The circuit of claim 1 , wherein P is 4 for frequencies less than about 267 MHz and 2 for frequencies greater than about 267 MHz, and wherein the set frequency is about 1 GHz.
5. A method of providing a clock frequency with an overclocking step resolution that is not a multiple of the clock frequency, comprising:
generating a VCO clock signal with a CPU PLL with a fractional N-divider feedback circuit;
frequency dividing the VCO clock signal by P in a P-divider;
setting P and parameters to the fractional N-divider in relation to the clock frequency in order to obtain the overclocking step resolution while keeping a frequency of the VCO clock signal below a set frequency.
6. The method of claim 5 , wherein the overclocking step resolution is 1 MHz.
7. The method of claim 5 , wherein the set frequency is about 1 GHz.
8. The method of claim 7 , wherein P is set to 4 for frequencies less than about 267 MHz and set to 2 for frequencies greater than about 267 MHz.
9. The method of claim 8 , wherein an N value of the fractional N-divider is adjusted according to the value of P.