IP Library Granted Patent US 7,419,748
Granted Patent B1
US 7,419,748 · App. 10/925,606 · Granted Sep 2, 2008

Photomask with reduced electrostatic discharge defects

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Quick Facts
Patent No.
US 7,419,748
App. No.
10/925,606
Granted
Sep 2, 2008
Kind
B1
Abstract

A photomask and a method for forming a photomask are disclosed in which the photomask pattern is modified to bridge features that are likely to produce electrostatic discharge related defects. In one embodiment those adjacent features that are closely spaced together and have a high surface area differential, are bridged using a bridge that has a width less than the minimum optical resolution of the photolithography process.

Claims (35)

1. A method for preventing electrostatic discharge related defects in a photomask comprising:

determining the surface area differential between adjacent features in a die region of a photomask pattern; and

connecting the adjacent features in the die region of the photomask pattern that are separated by a minimum distance that is less than 0.40 microns and that have a surface area differential that is greater than an area threshold using a bridge that has a width that is less than the minimum optical resolution of the photomask.

2. The method of claim 1 wherein the bridge only extends between the connected adjacent features.

3. The method of claim 2 further comprising:

forming a modified photomask pattern that includes the bridge; and

fabricating a photomask using the modified photomask pattern.

4. The method of claim 3 wherein the modified photomask pattern comprises an image that is stored in a pattern data file.

5. The method of claim 3 wherein the photomask comprises a reticle that includes a glass substrate and a pellicle that is coupled to the glass substrate.

6. The method of claim 2 wherein the area threshold is 650 square microns.

7. The method of claim 2 wherein the area threshold is 500 square microns.

8. A method for forming a photomask to be used in a photolithography process comprising:

determining the minimum distance between adjacent features in a die region of a photomask pattern;

determining the surface area differential of the adjacent features in the die region of the photomask pattern; and

connecting the adjacent features in the die region of the photomask pattern that have a minimum distance that is less than a first threshold and that have a surface area differential that is greater than a second threshold using bridges having a width that is less than the minimum optical resolution of the photolithography process.

9. The method of claim 8 wherein the bridges only extend between the adjacent features in the die region of the photomask pattern that have a minimum distance that is less than the first threshold and that have a surface area differential that is greater than the second threshold.

10. The method of claim 9 wherein the first threshold is less than or equal to 0.40 microns.

11. The method of claim 8 further comprising:

forming a modified photomask pattern that includes the bridges connecting the adjacent features; and

fabricating a photomask using the modified photomask pattern.

12. The method of claim 11 wherein the fabricating a photomask further comprises patterning an opaque layer of the photomask using the modified photomask pattern.

13. The method of claim 8 the second threshold is greater than or equal to 500 square microns.

14. A photomask for exposing an integrated circuit design in a photolithography process comprising:

a non-opaque substrate; and

a patterned opaque layer that overlies the substrate, the patterned opaque layer including bridges having a width that is less than the minimum optical resolution of the photolithography process, a single one of the bridges extending between adjacent features in a die area of the patterned opaque layer that are separated by a minimum distance that is less than 0.40 microns and that have a surface area differential that is greater than an area threshold.

15. The photomask of claim 14 wherein the bridges do not extend between any adjacent features in the die area of the patterned opaque layer that have a minimum distance that is greater than 0.40 microns.

16. The photomask of claim 14 wherein the bridges do not extend between any adjacent features in the die area of the patterned opaque layer that have a surface area differential that is not greater than the area threshold.

17. The photomask of claim 16 wherein only the adjacent features in the die region of the patterned opaque layer that that are separated a minimum distance that is less than a distance threshold are connected using the bridges, wherein the distance threshold is less than 0.40 microns.

18. The photomask of claim 14 wherein the area threshold is 500 square microns.

19. A computer-readable medium having computer-executable instructions for performing a method for forming a photomask pattern to be used in a photolithography process, comprising:

determining the minimum distance between adjacent features in a die region of a photomask pattern;

determining the surface area differential of the adjacent features in the die region of the photomask pattern; and

connecting the adjacent features in the die region of the photomask pattern that have a minimum distance that is less than a first threshold and that have a surface area differential that is greater than a second threshold using bridges having a width that is less than the minimum optical resolution of the photolithography process.

20. A computer-readable medium as described in claim 19 wherein the bridges only extend between the adjacent features in the die region of the photomask pattern that have a minimum distance that is less than the first threshold and that have a surface area differential that is greater than the second threshold.

21. A computer-readable medium as described in claim 19 wherein the first threshold is 0.20 microns and the second threshold is 650 square microns.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2004
From: AHN, JAE-GYUNG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 015762/0150 →