IP Library Granted Patent US 7,782,143
Granted Patent B2
US 7,782,143 · App. 11/683,800 · Granted Aug 24, 2010

Phase locked loop and delay locked loop with chopper stabilized phase offset

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Quick Facts
Patent No.
US 7,782,143
App. No.
11/683,800
Granted
Aug 24, 2010
Kind
B2
Abstract

A control circuit includes a phase frequency detector that receives a reference phase Φ REF (signal) as an input and a feedback phase Φ FBK (signal) as control feedback. A voltage controlled oscillator is in electrical communication with the phase frequency detector. The VCO provides an output and the feedback phase Φ FBK (signal). An auxiliary feedback loop receives error phase Φ E (signal) from each of the reference phase Φ REF (signal) and the feedback phase Φ FBK (signal). The auxiliary feedback loop provides an adjustment signal to the control circuit to correct for static phase offset.

Claims (27)

1. A control circuit comprising:

A phase detector that receives a reference phase φ REF (signal) as an input and a feedback phase φ FBK (signal) as control feedback;

A voltage controlled oscillator (VCO) in electrical communication with the phase detector, the VCO providing an output and the feedback phase φ FBK (signal), the phase detector and the VCO forming at least a portion of a main loop; and

An auxiliary feedback loop having a phase-frequency detector that, continuously and simultaneously with the phase detector of the main loop, receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal), the auxiliary feedback loop continuously providing an adjustment signal to the main loop that corrects for static phase offset;

wherein the auxiliary feedback loop includes a charge-pump and an input modulator that receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal), the reference phase φ REF (signal) and the feedback phase φ FBK (signal) are compared to determine an error phase signal, the error phase signal is amplified by the phase-frequency detector and the charge-pump, and wherein an output of the charge-pump is rectified and filtered.

2. The control circuit according to claim 1 , wherein the auxiliary feedback loop includes a difference amplifier.

3. The control circuit according to claim 1 , wherein the main loop is a phase locked loop (PLL).

4. The control circuit according to claim 1 , wherein the control circuit is a zero delay buffer (ZDB) and the auxiliary feedback loop provides chopper stabilization of static phase offset (SPO) of the ZDB.

5. The control circuit according to claim 1 , further comprising:

a charge pump in electrical communication with the phase frequency detector, the phase frequency detector providing up and down pulse signals to the charge-pump; and

a loop filter in electrical communication with the charge pump, the charge pump providing source current I Source to the loop filter receiving sink current I Sink back from a node that is coupled to the loop filter, the voltage controlled oscillator (VCO) in electrical communication with the loop filter.

6. A control circuit comprising:

A primary phase detector that receives a reference phase φ REF (signal) as an input and a feedback phase φ FBK (signal) as control feedback;

A variable delay that receives the reference phase φ REF (signal), the variable delay being controlled by the phase detector, the variable delay providing an output and the feedback phase φ FBK (signal), the phase detector and the variable delay forming at least a portion of a main loop; and

An auxiliary feedback loop having a phase-frequency detector that, continuously and simultaneously with the phase detector of the main loop, receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal), the auxiliary feedback loop continuously providing an adjustment signal to the main loop that corrects for static phase offset;

wherein the auxiliary feedback loop includes a charge-pump and an input modulator that receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal), the reference phase φ REF (signal) and the feedback phase φ FBK (signal) are compared to determine an error phase signal, the error phase signal is amplified by the phase-frequency detector and the charge-pump, and wherein an output of the charge-pump is rectified and filtered.

7. The control circuit according to claim 6 , wherein the auxiliary feedback loop includes a difference amplifier.

8. The control circuit according to claim 6 , wherein the main loop is a delay locked loop (DLL).

9. The control circuit according to claim 8 , wherein the control circuit is a zero delay buffer (ZDB) and the auxiliary feedback loop provides chopper stabilization of static phase offset (SPO) of the ZDB.

10. A control circuit comprising:

A primary phase detector that receives a reference phase φ REF (signal) as an input and a feedback phase φ FBK (signal) as control feedback;

A voltage controlled oscillator (VCO) in electrical communication with the primary phase detector, the VCO providing an output and the feedback phase φ FBK (signal), the phase detector and the VCO forming at least a portion of a main loop; and

An auxiliary phase detector that, continuously and simultaneously with the primary phase detector, receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal) from an input modulator that receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal), the auxiliary phase detector providing an adjustment signal to the main loop that corrects for static phase offset, wherein the reference phase φ REF (signal) and the feedback phase φ FBK (signal) are compared to determine an error phase signal, the error phase signal is amplified by the auxiliary phase detector and a charge-pump, and wherein an output of the charge-pump is rectified and filtered.

11. A control circuit comprising:

A phase detector that receives a reference phase φ REF (signal) as an input and a feedback phase φ FBK (signal) as control feedback;

A variable delay that receives the reference phase φ REF (signal), the variable delay being controlled by the phase detector, the variable delay providing an output and the feedback phase φ FBK (signal), the phase detector and the variable delay forming at least a portion of a main loop; and

An auxiliary phase detector that, continuously and simultaneously with the primary phase detector, receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal) from an input modulator that receives the reference phase φ REF (signal) and the feedback phase φ FBK (signal), the auxiliary phase detector providing an adjustment signal to the main loop that corrects for static phase offset, wherein the reference phase φ REF (signal) and the feedback phase φ FBK (signal) are compared to determine an error phase signal, the error phase signal is amplified by the auxiliary phase detector and a charge-pump, and wherein an output of the charge-pump is rectified and filtered.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2007
From: CLEMENTI, DANIEL M.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 019735/0649 →