Integrated circuit package encapsulating a hermetically sealed device
An integrated circuit package is disclosed having a semiconductor chip, a device supported by the semiconductor chip, and a molding compound sealing the semiconductor chip and the device together as a composite package. A method of manufacturing the package is also disclosed.
1. An integrated circuit package, comprising:
a semiconductor chip having a surface;
a first conductor provided on the surface of the semiconductor chip;
a hermetically sealed device supported by the semiconductor chip and provided on the surface of the semiconductor chip;
a second conductor extending from a portion of the hermetically sealed device to the first conductor; and
a molding compound sealing the semiconductor chip and the hermetically sealed device inside the package.
2. An integrated circuit package according to claim 1 , wherein the hermetically sealed device includes a cavity.
3. An integrated circuit package according to claim 1 , wherein the semiconductor chip is supported by a substrate, the substrate being selected from silicon, quartz, ceramic, glass epoxy, and a metal lead frame.
4. An integrated circuit package according to claim 1 , further comprising electrical contacts disposed on the outside of the package.
5. An integrated circuit package according to claim 4 , wherein the electrical contacts include solder balls.
6. An integrated circuit package according to claim 4 , wherein the semiconductor chip is electrically-interconnected to the electrical contacts.
7. An integrated circuit package according to claim 6 , wherein the semiconductor chip is electrically-interconnected to the electrical contacts with electrical wires attached to wiring portions on the substrate.
8. An integrated circuit package according to claim 4 , wherein the hermetically sealed device is electrically-interconnected to the electrical contacts with electrical wires attached to wiring portions on the substrate.
9. An integrated circuit package according to claim 1 , wherein the semiconductor chip is bonded to a substrate with an epoxy.
10. An integrated circuit package according to claim 1 , wherein the semiconductor chip is a digital signal processor chip.
11. An integrated circuit package according to claim 1 , wherein the semiconductor chip is a microprocessor.
12. An integrated circuit package according to claim 1 , wherein the semiconductor chip is a media access controller.
13. An integrated circuit package according to claim 1 , wherein the hermetically sealed device is provided in direct contact with the semiconductor chip.
14. An integrated circuit package according to claim 1 , wherein a buffer material is disposed between the semiconductor chip and the hermetically sealed device.
15. An integrated circuit package according to claim 1 , wherein the hermetically sealed device includes a contact, the first conductor includes a bond pad, and the second conductor includes a wire, the wire connecting the bond pad to the contact.
16. An integrated circuit package according to claim 1 , wherein the hermetically sealed device and the semiconductor chip are electrically-interconnected without wires.
17. An integrated circuit package according to claim 1 , wherein the hermetically sealed device includes a frequency source.
18. An integrated circuit package according to claim 1 , wherein the hermetically sealed device includes a resonator circuit.
19. An integrated circuit package according to claim 1 , wherein the hermetically sealed device is a programmable oscillator.
20. An integrated circuit package according to claim 1 , wherein the hermetically sealed device includes a surface acoustic wave structure.
21. An integrated circuit package according to claim 1 , wherein the hermetically sealed device includes a MEMs structure.
22. An integrated circuit package according to claim 21 , wherein the MEMs structure is a resonator.
23. An integrated circuit package according to claim 21 , wherein the MEMs structure is coupled to a surface acoustic wave structure.