Method and apparatus for burn-in of semiconductor devices
View Patent ↗A method and apparatus for burn-in of semiconductor devices is disclosed. A semiconductor device that includes built-in self test circuitry is coupled to a socket on a burn-in board. The burn in board and the semiconductor device are heated. Burn-in instructions can be transmitted to the semiconductor device through a JTAG terminal of the semiconductor device. Upon receiving a burn-in instruction through a JTAG terminal, the built-in self test circuitry is operable to perform one or more burn-in function. This allows for burn-in of a semiconductor device without any transfer of data through the data input terminals of the semiconductor device.
1. A semiconductor device comprising:
a memory array that includes memory cells, registers and mask cells;
data input terminals electrically coupled to the memory cells;
JTAG terminals; and
circuitry electrically coupled to the JTAG terminals and operable upon receiving an instruction through one of the JTAG terminals to perform a full burn-in routine of the memory array in which a zero and a one are written to each memory cell, a zero and a one are written to each register, a zero and a one are written to each mask cell, a horizontal stripe pattern is written to the memory cells, a horizontal stripe-bar pattern is written to the memory cells and a lookup loop is performed so as to cause alternating match lines to match and not match.
2. A semiconductor device as recited in claim 1 wherein the circuitry includes built-in self test circuitry and wherein the semiconductor device includes a plurality of device-specific terminals, the built-in self test circuitry operable upon receiving a signal through one of the device-specific terminals to perform a full burn-in routine of the memory array in which a zero and a one are written to each memory cell, a zero and a one are written to each register a zero and a one are written to each mask cell, a horizontal stripe pattern is written to the memory cells, a horizontal stripe-bar pattern is written to the memory cells and a lookup loop is performed so as to cause alternating match lines to match and not match.
3. A semiconductor device as recited in claim 1 wherein the memory array is a Content Addressable Memory array.
4. A semiconductor device as recited in claim 1 wherein no data is required to be transmitted through the data input terminals in order for the circuitry to perform the full burn-in routine.
5. A semiconductor device as recited in claim 1 wherein the JTAG terminals comprise a test data input terminal, a test data output terminal, a test reset input terminal, a test mode select terminal and a test clock input terminal.
6. A semiconductor device as recited in claim 1 wherein said circuitry performs a full burn-in routine upon receipt of a single instruction through one of said JTAG terminals.
7. A method for performing burn-in comprising:
coupling a semiconductor device that includes JTAG terminals, test circuitry and a memory array having memory cells, registers and mask cells to a burn-in board;
heating the semiconductor device and the burn-in board; and
sending an instruction to one of the JTAG terminals while the semiconductor device and the burn-in board are heated, the test circuitry operable upon receiving the instruction to perform a full burn-in function routine of the memory array in which a zero and a one are written to each memory cell, a zero and a one are written to each register, a zero and a one are written to each mask cell, a horizontal stripe pattern is written to the memory cells, a horizontal stripe-bar pattern is written to the memory cells and a lookup loop is performed so as to cause alternating match lines to match and not match.
8. A method as recited in claim 7 wherein the semiconductor device includes a plurality of data input terminals, and wherein no data is required to be transmitted through the data input terminals in order to write data to the memory cells.
9. A method as recited in claim 7 wherein the semiconductor device includes a plurality of device-specific terminals, the semiconductor device operable upon receiving a signal through one of the device-specific terminals to perform a full burn-in routine of the memory array in which a zero and a one are written to each memory cell, a zero and a one are written to each register, a zero and a one are written to each mask cell, a horizontal stripe pattern is written to the memory cells, a horizontal stripe-bar pattern is written to the memory cells and a lookup loop is performed so as to cause alternating match lines to match and not match.
10. A method as recited in claim 7 wherein the JTAG terminals include a test data input terminal and wherein the instruction is transmitted to the test data input terminal.
11. A method as recited in claim 7 further comprising coupling the burn-in board to a burn-in driver, and wherein the burn-in driver is operable to send the instruction to one of the JTAG terminals.
12. The method as recited in claim 7 wherein the semiconductor device comprises a Content Addressable Memory (CAM).