Calibration method and apparatus for phase locked loop circuit
View Patent ↗An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, includes a calibration circuit. The calibration circuit is coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator. The calibration circuit includes a counting circuit for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal. The calibration circuit also includes a selection block for performing a convergence test using the counted number of fast clock cycles, N, and M. The selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.
1. An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, the integrated circuit device comprising:
a calibration circuit coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator, the calibration circuit including:
a counting circuit operable for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal; and
a selection block operable for performing a convergence test using the counted number of fast clock cycles, N, and M, wherein the selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.
2. The apparatus of claim 1 wherein M is an integer power of 2.
3. The apparatus of claim 1 wherein the convergence test computes a difference between the counted number of fast clock cycles and N·M.
4. The apparatus of claim 3 wherein the convergence test is an inequality test between the counted number of fast clock cycles and N·M.
5. The apparatus of claim 3 wherein the convergence test circuit further comprises a shift register for computing the product of N and M.
6. The apparatus of claim 1 wherein the calibration circuit executes a binary search to select the calibrated frequency band.
7. The apparatus of claim 1 wherein the variable frequency oscillator is a digitally controlled oscillator.
8. A method for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a first divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, the method comprising:
coupling a calibration circuit to the reference clock signal input, the input of the variable frequency oscillator and to the output of the variable frequency oscillator;
selecting a frequency band of a plurality of frequency bands as a candidate calibration frequency band;
counting the number of cycles of the fast clock signal over a period of time defined by a number of the reference clock cycles (M); and
performing a convergence test using the counted number of fast clock cycles, N, and M;
selecting another frequency band of the plurality of frequency bands as the candidate calibration frequency band in accordance with the results of the convergence test; and
continuing the counting, the performing and the selecting another frequency band for a plurality of iterations to identify a last candidate calibration frequency band for the phase locked loop circuit.
9. The method of claim 8 wherein the performing a convergence test computes a difference between the counted number of fast clock cycles and N·M.
10. The method of claim 9 wherein the performing a convergence test performs an inequality test between the counted number of fast clock cycles and N·M.
11. The method of claim 8 wherein the performing a convergence test is a function of the counted number of fast clock cycles and N·M, wherein M is an integer power of 2 and further wherein N·M is computed using a shift register.
12. The method of claim 8 further comprising:
initiating normal operation of the PLL circuit, the variable frequency oscillator configured to operate using the last candidate calibration frequency band as the calibrated frequency band.
13. The method of claim 12 further comprising:
decoupling the calibration circuit from the reference clock signal input and the output of the variable frequency oscillator.
14. The method of claim 8 wherein the PLL comprises a second divider configured to divide the fast clock signal by a divisor (K) wherein K # N.
15. An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, a first divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, and a second divider configured to divide the fast clock signal by a divisor (K) wherein K≠N, the integrated circuit device comprising:
a calibration circuit coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator, the calibration circuit including:
a counting circuit operable for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal; and
a selection block operable for performing a convergence test using the counted number of fast clock cycles, N, and M, wherein the selection block generates the frequency band selection signal in accordance with the results of the convergence test to select a next candidate calibrated frequency band.
16. The apparatus of claim 15 wherein N is an integer power of 2.
17. The apparatus of claim 15 wherein the convergence test computes a difference between the counted number of fast clock cycles and N·M.
18. The apparatus of claim 15 wherein the convergence test is an inequality test between the counted number of fast clock cycles and N·M.
19. The apparatus of claim 17 further comprising a shift register for computing N·M.
20. The apparatus of claim 15 wherein the calibration circuitry executes a binary search to select the calibrated frequency band.
21. The apparatus of claim 15 wherein the variable frequency oscillator is a digitally controlled oscillator.