On-die verification of resistor fabricated in CMOS process
An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.
1. An apparatus comprising:
a resistor fabricated on a die using a semiconductor process; and
a circuit fabricated on said die using said semiconductor process and configured to (i) generate a measurement voltage at a node of said resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to said measurement voltage, wherein (a) said codeword has a plurality of possible values and (b) a particular value of said possible values verifies that said voltage is between a plurality of threshold voltages.
2. The apparatus according to claim 1 , wherein said semiconductor process comprises a complementary metal-oxide-semiconductor process.
3. The apparatus according to claim 1 , wherein said resistor comprises two resistors (i) wired in parallel and (ii) each having a same resistance value.
4. The apparatus according to claim 1 , wherein said circuit comprises a plurality of capacitors alternately connected to and disconnected from said resistor at said frequency of said clock signal to generate said measurement voltage.
5. The apparatus according to claim 4 , wherein said circuit further comprises a plurality of switches each configured to discharge a respective one of said capacitors while said respective capacitor is disconnected from said resistor.
6. The apparatus according to claim 4 , wherein said circuit further comprises an amplifier configured to amplify said measurement voltage relative to a fixed voltage to generate a gain signal that has a range from above to below said fixed voltage.
7. The apparatus according to claim 6 , wherein said circuit further comprises a plurality of comparators configured to generate said codeword by comparing said gain signal to said threshold voltages.
8. The apparatus according to claim 1 , further comprising an additional resistor having a same resistance value as said resistor, wherein said additional resistor is used to generate a reference signal that depends on said same resistance value.
9. The apparatus according to claim 1 , wherein a resistance of said resistor is adjustable in response to a control signal to establish said particular value in said codeword.
10. The apparatus according to claim 1 , wherein each of said plurality of threshold voltages is adjustable in response to a control signal.
11. A method for verifying a resistor value, comprising the steps of:
generating a measurement voltage at a node of a resistor as a function of a capacitance value and a frequency of a clock signal, wherein said resistor is fabricated on a die using a semiconductor process; and
generating a codeword in response to said measurement voltage in a circuit fabricated on said die using said semiconductor process, wherein (i) said codeword has a plurality of possible values and (ii) a particular value of said possible values verifies that said voltage is between a plurality of threshold voltages.
12. The method according to claim 11 , wherein said semiconductor process comprises a complementary metal-oxide-semiconductor process.
13. The method according to claim 11 , wherein said resistor comprises two resistors (i) wired in parallel and (ii) each having a same resistance value.
14. The method according to claim 11 , further comprising the step of:
alternately connecting and disconnecting a plurality of capacitors to and from said resistor at said frequency of said clock signal to generate said measurement voltage.
15. The method according to claim 14 , further comprising the step of:
discharging each respective one of said capacitors while said respective capacitor is disconnected from said resistor.
16. The method according to claim 14 , further comprising the step of:
amplifying said measurement voltage relative to a fixed voltage to generate a gain signal that has a range from above to below said fixed voltage.
17. The method according to claim 16 , further comprising the step of:
generating said codeword by comparing said gain signal to said threshold voltages.
18. The method according to claim 11 , wherein (i) an additional resistor has a same resistance value as said resistor and (ii) said additional resistor is used to generate a reference signal that depends on said same resistance value.
19. The method according to claim 11 , further comprising the steps of:
adjusting a resistance of said resistor in response to a first control signal to establish said particular value in said codeword; and
adjusting each of said plurality of threshold voltages in response to a second control signal.
20. An apparatus comprising:
a controller configured to generate a clock signal; and
a circuit fabricated on a die using a semiconductor process, comprising a resistor and configured to (i) generate a measurement voltage at a node of said resistor as a function of a capacitance value and a frequency of said clock signal and (ii) transfer to said controller a codeword generated in response to said measurement voltage, wherein (a) said codeword has a plurality of possible values and (b) a particular value of said possible values verifies that said voltage is between a plurality of threshold voltages.