MEMS-based frequency synthesizers with enhanced temperature compensation

1. A frequency synthesizer, comprising:

a phase-locked loop (PLL) frequency generator configured to generate a periodic output signal in response to a periodic input signal, said PLL frequency generator comprising a feedback divider responsive to a feedback divider code; and

a code generation circuit configured to generate the feedback divider code, said code generation circuit comprising:

an analog-to-digital (ADC) converter configured as a cascaded arrangement of a delta-sigma modulator and a multi-stage digital filter configured to generate a corresponding plurality of divider codes from the multiple stages thereof; and

a selection circuit configured to use a first of the plurality divider codes to generate the feedback divider code when said PLL frequency generator is unlocked and use a second of the plurality of divider codes to generate the feedback divider code when said PLL frequency generator is locked.

2. The frequency synthesizer of claim 1 , wherein the delta-sigma modulator is a 2nd or higher order modulator.

3. The frequency synthesizer of claim 1 , wherein the multi-stage digital filter comprises a sinc filter configured to generate the first of the plurality of divider codes.

4. The frequency synthesizer of claim 3 , wherein the multi-stage digital filter further comprises a cascaded arrangement of a plurality of halfband finite impulse response (FIR) filters.

5. The frequency synthesizer of claim 4 , wherein the second of the plurality of divider codes is generated by one of the plurality of halfband finite impulse response (FIR) filters.

6. The frequency synthesizer of claim 1 , wherein the multi-stage digital filter comprises a cascaded arrangement of a plurality of halfband finite impulse response (FIR) filters.

7. The frequency synthesizer of claim 6 , wherein the second of the plurality of divider codes is generated by one of the plurality of halfband finite impulse response (FIR) filters.

8. The frequency synthesizer of claim 1 , further comprising a microelectromechanical-based frequency generator configured to generate the periodic input signal.

9. The frequency synthesizer of claim 8 , further comprising a temperature sensor configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the microelectromechanical-based frequency generator.

10. The frequency synthesizer of claim 9 , wherein the ADC converter is responsive to the temperature measurement signal.

11. The frequency synthesizer of claim 9 , wherein the microelectromechanical-based frequency generator comprises a microelectromechanical resonator; and wherein the temperature sensor is configured to generate a temperature measurement signal in response to detecting a temperature of the microelectromechanical resonator.

12. A frequency synthesizer, comprising:

a frequency generator configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent code;

a temperature sensor configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer; and

a control circuit configured to generate the temperature-dependent code in response to the temperature measurement signal, said control circuit comprising:

a cascaded arrangement of an oversampled data converter and a multi-stage digital filter configured to generate a plurality of codes from respective ones of the digital filter stages; and

a selection circuit configured to use at least first and second ones of the plurality of codes in sequence during first and second consecutive time intervals, respectively, to generate the temperature-dependent code.

13. The frequency synthesizer of claim 12 , wherein the oversampled data converter is a 2nd or higher order delta-sigma modulator.

14. The frequency synthesizer of claim 12 , wherein the multi-stage digital filter comprises a sinc filter configured to generate the first of the plurality of codes.

15. The frequency synthesizer of claim 14 , wherein the multi-stage digital filter further comprises a cascaded arrangement of a plurality of halfband finite impulse response (FIR) filters.

16. The frequency synthesizer of claim 15 , wherein the second of the plurality of codes is generated by one of the plurality of halfband finite impulse response (FIR) filters.

17. The frequency synthesizer of claim 16 , wherein said frequency generator comprises a locked-loop integrated circuit; and wherein said selection circuit is configured to use the first of the plurality of codes when the locked-loop integrated circuit is unlocked and the second of the plurality of codes when the locked-loop integrated circuit is locked.

18. The frequency synthesizer of claim 12 , wherein said frequency generator comprises a locked-loop integrated circuit; and wherein said selection circuit is configured to use the first of the plurality of codes when the locked-loop integrated circuit is unlocked and the second of the plurality of codes when the locked-loop integrated circuit is locked.

19. The frequency synthesizer of claim 12 , wherein the frequency synthesizer further comprises a microelectromechanical-based frequency generator configured to generate the periodic input signal; and wherein said temperature sensor is configured to detect a temperature of at least a portion of the microelectromechanical-based frequency generator.

20. The frequency synthesizer of claim 19 , wherein the microelectromechanical-based frequency generator comprises a microelectromechanical resonator; and wherein said temperature sensor is configured to detect a temperature of the microelectromechanical resonator.