IP Library Granted Patent US 9,905,995
Granted Patent B2
US 9,905,995 · App. 15/252,877 · Granted Feb 27, 2018

Adjustable termination circuit for high speed laser driver

Inventors: Samuel Aloysius Steidl (Palo Alto, CA); Emad Afifi (San Jose, CA)
Assignee: Integrated Device Technology, Inc.
H01S5/0427H01S5/06226
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Quick Facts
Patent No.
US 9,905,995
App. No.
15/252,877
Granted
Feb 27, 2018
Kind
B2
Abstract

Disclosed is a circuit having a high speed laser driver circuit, a semiconductor laser electrically connected to the high speed laser driver circuit, and an adjustable termination circuit electrically connected between the high speed laser driver circuit and the semiconductor laser, where the adjustable termination circuit is configured to control an output impedance seen by the semiconductor laser as a function of an input current provided to the adjustable termination circuit.

Claims (26)

1. A circuit comprising:

a high speed laser driver circuit;

a semiconductor laser electrically connected to the high speed laser driver circuit; and

an adjustable termination circuit electrically connected between the high speed laser driver circuit and the semiconductor laser, wherein the adjustable termination circuit is configured to control an output impedance seen by the semiconductor laser as a function of an input current provided to the adjustable termination circuit,

wherein the adjustable termination circuit comprises an operational amplifier configured to drive an input offset voltage, across inputs to the operational amplifier, to zero,

wherein one of the inputs to the operational amplifier is electrically connected in series between a power source and an offset resistor,

wherein the power source is configured to provide an input current to the offset resistor, thereby generating the input offset voltage across the inputs of the operational amplifier, and

wherein the operational amplifier comprises an output electrically connected to a base terminal of a transistor, wherein an emitter terminal of the transistor is electrically connected to a termination resistor.

2. The circuit of claim 1 , wherein the termination resistor is electrically connected between the transistor and the semiconductor laser.

3. The circuit of claim 2 , wherein the operational amplifier is configured to induce the transistor to provide a termination current in response to the input offset voltage at the input of the operational amplifier.

4. The circuit of claim 3 , wherein the transistor is a bipolar transistor having a transistor impedance at the emitter terminal that is a function of the termination current.

5. The circuit of claim 3 , wherein the transistor is a NMOS transistor having a transistor impedance at a source terminal that is a function of the termination current.

6. The circuit of claim 4 , wherein the output impedance seen by the semiconductor laser is equal to the summation of an impedance of the termination resistor and the transistor impedance.

7. The circuit of claim 5 , wherein the output impedance seen by the semiconductor laser is equal to the summation of an impedance of the termination resistor and the transistor impedance.

8. An adjustable termination circuit for controlling an output impedance seen by a semiconductor laser, wherein the adjustable termination circuit is electrically connected between a high speed laser driver circuit and the semiconductor laser, wherein the adjustable termination circuit comprises:

a power source configured to provide an input current;

an offset resistor;

an operational amplifier configured to drive an input offset voltage, across inputs to the operational amplifier, to zero, wherein one of the inputs to the operational amplifier is electrically connected in series between the power source and the offset resistor such that the input current provided by the power source to the offset resistor generates the input offset voltage across the inputs of the operational amplifier;

a transistor having a base terminal electrically connected to an output of the operational amplifier; and

a termination resistor electrically connected between an emitter terminal of the transistor and the semiconductor laser,

wherein the operational amplifier is configured to induce the transistor to provide a termination current in response to the input offset voltage at the input of the operational amplifier, wherein a transistor impedance of the transistor is based on the termination current, and

wherein the output impedance seen by the semiconductor laser is a function of the transistor impedance and is therefore adjustable as a function of the input current.

9. The adjustable termination circuit of claim 8 , wherein the transistor is a bipolar transistor having a transistor impedance at the emitter terminal that is a function of the termination current.

10. The adjustable termination circuit of claim 8 , wherein the transistor is a NMOS transistor having a transistor impedance at a source terminal that is a function of the termination current.

11. The adjustable termination circuit of claim 9 , wherein the output impedance seen by the semiconductor laser is equal to the summation of an impedance of the termination resistor and the transistor impedance.

12. The adjustable termination circuit of claim 10 , wherein the output impedance seen by the semiconductor laser is equal to the summation of an impedance of the termination resistor and the transistor impedance.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2017
From: GIGPEAK, INC.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 043207/0576 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2016
From: STEIDL, SAMUEL ALOYSIUS; AFIFI, EMAD
To: GIGPEAK, INC.
Reel/Frame 039604/0020 →
Continuity (2)
Provisional Application 62213024 · Sep 1, 2015
Related Publication 20170063036A1 · Mar 2, 2017