Gate structures having sidewall spacers using selective deposition and method of forming the same
View Patent ↗Gate stacks with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling is disclosed, along with a method of forming the gate structures over a semiconductor substrate. A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack 24 having a sidewall is formed over the gate dielectric layer. The gate stack 24 comprises a conductive layer 28 and a hard mask 30 overlying the conductive layer 28 . A liner 32 is selectively deposited over the gate stack 24 such that the liner 32 is deposited on the hard mask 30 at a rate lower than the rate of deposition on the conductive layer 28 . Thus, the liner 32 is substantially thinner on the hard mask 30 than on the conductive layer 28 . A nitride spacer is formed over 34 the liner 32 . A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks and substantially free of voids.
1. A method of manufacturing a semiconductor device on a semiconductor substrate, comprising:
forming a gate dielectric on the semiconductor substrate;
forming a gate stack overlying the gate dielectric, the gate stack having a sidewall,
wherein the gate stack comprises a conductive layer and a hard mask overlying the conductive layer;
selectively depositing a liner over the gate stack such that the liner is deposited on the hard mask at a rate lower than the rate of deposition on the conductive layer, so that the liner is thinner on the hard mask than on the conductive layer; and
forming a nitride spacer over the liner.
2. The method of claim 1 , wherein said forming a nitride spacer comprises:
forming a layer of nitride spacer material conformally over the liner; and
etching back the layer of nitride spacer material.
3. The method of claim 1 , wherein the liner is deposited on the hard mask at a rate approximately one-fifth the rate of deposition on the conductive layer.
4. The method of claim 1 , wherein the liner is deposited selectively on the conductive layer in a thickness at least twice a thickness of deposition on the hard mask.
5. The method of claim 1 , wherein said liner is formed of oxide.
6. A method of manufacturing a semiconductor device on a semiconductor substrate, comprising:
forming at least two adjacent gate stacks over the substrate, the adjacent gate stacks each having a sidewall opposing each other,
wherein each of the gate stacks comprises a conductive layer and a hard mask overlying the conductive layer;
selectively depositing a liner over the gate stacks, so that the liner is thicker on the conductive layer than on the hard mask; and
forming adjacent at least two nitride spacers on the liner, overlying the opposing sidewalls,
wherein the liner is deposited over the hard mask at a rate lower than the rate of deposition on the conductive layer.
7. The method of claim 6 , wherein the liner is deposited on the hard mask at a rate approximately one-fifth the rate of deposition on the conductive layer.
8. The method of claim 6 , wherein the liner is deposited selectively on the conductive layer in a thickness at least twice a thickness of deposition on the hard mask.
9. The method of claim 6 , wherein said forming adjacent nitride spacers comprises:
forming a layer of nitride spacer material conformally over the liner, and etching back the layer of nitride spacer material.
10. The method of claim 6 , wherein the adjacent nitride spacers have top, middle, and bottom spaces therebetween, and wherein the bottom space is substantially shorter than the middle space.