IP Library Granted Patent US 8,501,515
Granted Patent B1
US 8,501,515 · App. 13/035,148 · Granted Aug 6, 2013

Methods of forming micro-electromechanical resonators using passive compensation techniques

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Quick Facts
Patent No.
US 8,501,515
App. No.
13/035,148
Granted
Aug 6, 2013
Kind
B1
Abstract

Methods of forming electro-micromechanical resonators provide passive temperature compensation of semiconductor device layers used therein. A first substrate is provided that includes a first electrically insulating temperature compensation layer on a first semiconductor device layer. A step is performed to bond the first electrically insulating temperature compensation layer to a second substrate containing the second electrically insulating temperature compensation layer therein, to thereby form a relatively thick temperature compensation layer. A piezoelectric layer is formed on the first electrically insulating temperature compensation layer and at least a first electrode is formed on the piezoelectric layer.

Claims (13)

1. A method of forming a micro-electromechanical resonator, comprising:

forming a first substrate comprising a first buried insulating layer, a first semiconductor device layer on the first buried insulating layer and a first electrically insulating temperature compensation layer on the first semiconductor device layer;

forming a second substrate comprising a second buried insulating layer, a second semiconductor device layer on the second buried insulating layer and a second electrically insulating temperature compensation layer on the second semiconductor device layer;

bonding the second electrically insulating temperature compensation layer directly to the first electrically insulating temperature compensation layer; then

removing the second buried insulating layer to thereby expose the second semiconductor device layer;

forming a bottom electrode on the second semiconductor device layer;

forming a piezoelectric layer on the bottom electrode and on first and second electrically insulating temperature compensation layers;

forming at least a first electrode on the piezoelectric layer, which extends between the first electrode and the bottom electrode;

selectively etching the piezoelectric layer, the second semiconductor device layer, the first and second electrically insulating temperature compensation layers and the first semiconductor device layer in sequence to expose the first buried insulating layer; and

removing at least portion of the buried insulating layer from the first semiconductor device layer to thereby define a suspended resonator body comprising first portions of the piezoelectric layer, the first and second second semiconductor device layers and the first and second electrically insulating temperature compensation layers, which extend between the first semiconductor device layer and the second semiconductor device layer.

2. The method of claim 1 , wherein said bonding comprises fusion bonding the second electrically insulating temperature compensation layer directly to the first electrically insulating temperature compensation layer.

3. The method of claim 1 , wherein said bonding comprises fusion bonding the second electrically insulating temperature compensation layer directly to the first electrically insulating temperature compensation layer at a temperature of about 1000° C.

4. The method of claim 1 , wherein the first and second semiconductor device layers are silicon device layers; wherein the first and second electrically insulating temperature compensation layers are silicon dioxide layers; and wherein a combined thickness of the first and second electrically insulating temperature compensation layers is sufficient to provide substantially complete temperature compensation to the first and second semiconductor device layers.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2011
From: PAN, WANLING
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 025871/0084 →