Packet processors having comparators therein that determine non-strict inequalities between applied operands
View Patent ↗An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C o (or its complement), where: C o = ( … ( ( C i ( A 0 + B 0 _ ) + A 0 B 0 _ ) ( A 1 + B 1 _ ) + A 1 B 1 _ ) … ( A n - 2 + B n - 2 _ ) + A n - 2 B n - 2 _ ) ( A n - 1 + B n - 1 _ ) + A n - 1 B n - 1 _ , “n” is a positive integer greater than one and C i is a control input signal that specifies an interpretation to be given to the control output signal C o .
1. An integrated circuit comparator, comprising:
at least one n-bit comparator cell configured to determine a non-strict inequality between a first n-bit operand A[n−1, . . . , 0] and a second n-bit operand B[n−1, . . . , 0], according to the following expression and boolean equivalents of the following expression:
C
o
=
(
…
(
(
C
i
(
A
0
+
B
0
_
)
+
A
0
B
0
_
)
(
A
1
+
B
1
_
)
+
A
1
B
1
_
)
…
(
A
n
-
2
+
B
n
-
2
_
)
+
A
n
-
2
B
n
-
2
_
)
(
A
n
-
1
+
B
n
-
1
_
)
+
A
n
-
1
B
n
-
1
_
,
where n is a positive integer greater than one, C i is a control input signal and C o or its complement is a control output signal, said at least one n-bit comparator cell comprising:
a first pair of MOS transistors electrically connected in parallel between first and second nodes and having gate terminals that receive operand bit A 0 and a complement of operand bit B 0 , respectively;
a second pair of MOS transistors electrically connected in parallel between the second node and a third node and having gate terminals that receive operand bit A 1 and a complement of operand bit B 1 , respectively;
a third pair of MOS transistors electrically connected in series between the second node and a fourth node and having gate terminals that receive the operand bit A 0 and the complement of operand bit B 0 , respectively;
a fourth pair of MOS transistors electrically connected in series between the third node and the fourth node and having gate terminals that receive the operand bit A 1 and the complement of operand bit B 1 , respectively; and
a MOS input transistor having a first current carrying terminal electrically connected to the first node, a second current carrying terminal electrically connected to the fourth node and a gate terminal that receives the control input signal C i .
2. The comparator of claim 1 , wherein said at least one n-bit comparator cell is configured so that each one bit increase in “n” results in a four transistor increase in cell size for “n” in at least the following range: 2<n<6.
3. The comparator of claim 1 , wherein said at least one n-bit comparator cell is an M-transistor cell, where M is a positive integer in a range from 4n+2 to 4n+6.
4. The comparator of claim 3 , wherein said at least one n-bit comparator cell is configured so that each one bit increase in “n” results in a four transistor increase in cell size for “n” in at least the following range: 2<n<6.
5. An integrated circuit comparator, comprising:
at least one n-bit comparator cell configured to determine a non-strict inequality between a first n-bit operand A[n−1, . . . , 0] and a second n-bit operand B[n−1, . . . , 0], according to the following expression and boolean equivalents of the following expression:
C
o
=
(
…
(
(
C
i
(
A
0
+
B
0
_
)
+
A
0
B
0
_
)
(
A
1
+
B
1
_
)
+
A
1
B
1
_
)
…
(
A
n
-
2
+
B
n
-
2
_
)
+
A
n
-
2
B
n
-
2
_
)
(
A
n
-
1
+
B
n
-
1
_
)
+
A
n
-
1
B
n
-
1
_
,
where n is a positive integer greater than one, C i is a control input signal and C o or its complement is a control output signal, said at least one n-bit comparator cell comprising:
a first pair of MOS transistors electrically connected in parallel between first and second nodes and having gate terminals that receive operand bit A 0 and a complement of operand bit B 0 , respectively;
a second pair of MOS transistors electrically connected in parallel between the second node and a third node and having gate terminals that receive operand bit A 1 and a complement of operand bit B 1 , respectively;
a third pair of MOS transistors electrically connected in series between the first node and a fourth node and having gate terminals that receive the operand bit A 0 and the complement of operand bit B 0 , respectively;
a fourth pair of MOS transistors electrically connected in series between the second node and the fourth node and having gate terminals that receive the operand bit A 1 and the complement of operand bit B 1 , respectively; and
a MOS input transistor having a first current carrying terminal electrically connected to the first node, a second current carrying terminal electrically connected to the fourth node and a gate terminal that receives the control input signal C i .
6. An integrated circuit comparator, comprising:
a comparator cell responsive to a control input signal and first and second multi-bit operands, said comparator cell configured to generate a control output signal that encodes a “≦” inequality between the first and second multi-bit operands when the control input signal is in a first logic state and encodes a “≧” inequality between the first and second multi-bit operands when the control input signal is in a second logic state;
wherein the first and second multi-bit operands equal A[n−1, . . . , 0] and B[n−1, . . . , 0], respectively; and
wherein said comparator cell comprises:
a first pair of MOS transistors electrically connected in parallel between first and second nodes and having gate terminals that receive operand bit A 0 and a complement of operand bit B 0 , respectively;
a second pair of MOS transistors electrically connected in parallel between the second node and a third node and having gate terminals that receive operand bit A 1 and a complement of operand bit B 1 , respectively;
a third pair of MOS transistors electrically connected in series between the second node and a fourth node and having gate terminals that receive the operand bit A 0 and the complement of operand bit B 0 , respectively;
a fourth pair of MOS transistors electrically connected in series between the third node and the fourth node and having gate terminals that receive the operand bit A 1 and the complement of operand bit B 1 , respectively; and
a MOS input transistor having a first current carrying terminal electrically connected to the first node, a second current carrying terminal electrically connected to the fourth node and a gate terminal that receives the control input signal.
7. The comparator of claim 6 , wherein said comparator cell is an n-bit comparator cell that is configured so that each one bit increase in “n” results in a four transistor increase in cell size for “n” in at least the following range: 2<n<6.
8. The comparator of claim 6 , wherein said comparator cell is an n-bit comparator cell having M transistors therein, where M is a positive integer in a range from 4n+2 to 4n+6, for “n” in at least the following range: 2<n<6.
9. The comparator of claim 8 , wherein the n-bit comparator cell is configured so that each one bit increase in “n” results in a four transistor increase in cell size for “n” in at least the following range: 2<n<6.
10. An integrated circuit comparator, comprising:
a comparator cell responsive to a control input signal and first and second multi-bit operands, said comparator cell configured to generate a control output signal that encodes a “≦” inequality between the first and second multi-bit operands when the control input signal is in a first logic state and encodes a “≧” inequality between the first and second multi-bit operands when the control input signal is in a second logic state;
wherein the first and second multi-bit operands equal A[n−1, . . . , 0] and B[n−1, . . . , 0], respectively; and
wherein said comparator cell comprises:
a first pair of MOS transistors electrically connected in parallel between first and second nodes and having gate terminals that receive operand bit A 0 and a complement of operand bit B 0 , respectively;
a second pair of MOS transistors electrically connected in parallel between the second node and a third node and having gate terminals that receive operand bit A 1 and a complement of operand bit B 1 , respectively;
a third pair of MOS transistors electrically connected in series between the first node and a fourth node and having gate terminals that receive the operand bit A 0 and the complement of operand bit B 0 , respectively;
a fourth pair of MOS transistors electrically connected in series between the second node and the fourth node and having gate terminals that receive the operand bit A 1 and the complement of operand bit B 1 , respectively; and
a MOS input transistor having a first current carrying terminal electrically connected to the first node, a second current carrying terminal electrically connected to the fourth node and a gate terminal that receives the control input signal.