Method and apparatus for queue concatenation

1. A method comprising:

routing on a per-channel basis both flow control and data in a first queue;

presenting said data at an egress of said first queue;

receiving said data at an ingress of a second queue; and

scheduling said data based on a second queue status signal.

2. The method of claim 1 wherein said data is selected from the group consisting of a packet, and packet fragments.

3. The method of claim 2 wherein said scheduling further comprises receiving a status signal from an external interface.

4. A machine-readable medium having stored thereon instructions, which when executed performs the method of claim 1 .

5. An apparatus comprising:

a first queue having an ingress and an egress, said ingress capable of receiving flow control and packet data; and

a second queue having an ingress and an egress, said ingress operatively coupled to said first queue egress, and said second queue egress capable of transmitting said flow control and said packet data.

6. The apparatus of claim 5 further comprising a port having an input and an output, said input capable of receiving flow control information and said output coupled to said second queue.

7. An apparatus comprising:

means for routing on a per-channel basis both flow control and data in a first queue;

means for presenting said data at an egress of said first queue;

means for receiving said data at an ingress of a second queue; and

means for scheduling said data based on a second queue status signal.

8. The apparatus of claim 7 wherein said data is selected from the group consisting of a packet, and packet fragments.

9. The apparatus of claim 8 wherein said means for scheduling further comprises means for receiving a status signal from an external interface.

10. An apparatus comprising:

a plurality of on-chip queues, each having an ingress, and an egress;

one or more flow control and data paths associated with each of said plurality of on-chip queues, wherein information from said one or more flow control and data paths flows through each said associated with each of said plurality of on-chip queues; and

one or more logic blocks which may selectively couple one or more of said plurality of on-chip queues said egress to one or more of said plurality of on-chip queues said ingress.

11. The apparatus of claim 10 further comprising an external signal input, said input coupled to said one or more logic blocks.