Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays
View Patent ↗A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access transistors electrically coupled to a pair of FIFO read bit lines and a third pair of access transistors electrically coupled to a pair of memory read bit lines. A direct path data transfer circuit is provided. This transfer circuit is configured to support a unidirectional data transfer path that extends from first storage nodes within the first SRAM element to second storage nodes within the second dual-port SRAM element. This transfer circuit is also responsive to a direct path word line signal.
1. A multi-port memory cell, comprising:
a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines;
a second dual-port SRAM element having a second pair of access transistors electrically coupled to a pair of FIFO read bit lines and a third pair of access transistors electrically coupled to a pair of memory read bit lines; and
a data transfer circuit responsive to a direct path word line signal, said data transfer circuit configured to support a unidirectional data transfer path extending from first storage nodes within said first SRAM element to second storage nodes within said second dual-port SRAM element.
2. The memory cell of claim 1 , where said data transfer circuit comprises:
a pair of pass transistors having gate terminals electrically connected to corresponding ones of the first storage nodes and first current carrying terminals electrically connected to corresponding ones of the second storage nodes; and a pull-down transistor having a current carrying terminal electrically connected to second current carrying terminals of said pair of pass transistors and a gate terminal responsive to the direct path word line signal.
3. The memory cell of claim 1 , where said first SRAM element comprises a dual-port SRAM element having a fourth pair of access transistors electrically coupled to a pair of memory write bit lines.
4. The memory cell of claim 3 , where said data transfer circuit comprises:
a pair of pass transistors having gate terminals electrically connected to corresponding ones of the first storage nodes and first current carrying terminals electrically connected to corresponding ones of the second storage nodes; and
a pull-down transistor having a current carrying terminal electrically connected to second current carrying terminals of said pair of pass transistors and a gate terminal responsive to the direct path word line signal.
5. A quad-port cache memory cell, comprising:
a first dual-port SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines and a second pair of access transistors electrically coupled to a pair of memory write bit lines;
a second dual-port SRAM element having a third pair of access transistors electrically coupled to a pair of FIFO read bit lines and a fourth pair of access transistors electrically coupled to a pair of memory read bit lines; and
a data transfer circuit disposed between said first dual-port SRAM element and said second dual-port SRAM element, said data transfer circuit responsive to a direct path word line signal and configured to support a unidirectional data transfer path extending from first storage nodes within said first dual-port SRAM element to second storage nodes within said second dual-port SRAM element.
6. The memory cell of claim 5 , where said data transfer circuit comprises:
a pair of pass transistors having gate terminals electrically connected to corresponding ones of the first storage nodes and first current carrying terminals electrically connected to corresponding ones of the second storage nodes; and
a pull-down transistor having a current carrying terminal electrically connected to second current carrying terminals of said pair of pass transistors and a gate terminal responsive to the direct path word line signal.
7. A multi-port cache memory cell, comprising:
a first dual-port memory element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines and a second pair of access transistors electrically coupled to a pair of memory write bit lines;
a second dual-port memory element having a third pair of access transistors electrically coupled to a pair of FIFO read bit lines and a fourth pair of access transistors electrically coupled to a pair of memory read bit lines; and
a data transfer circuit disposed between said first dual-port memory element and said second dual-port memory element, said data transfer circuit responsive to a direct path word line signal and configured to support a unidirectional data transfer path extending from first storage nodes within said first dual-port memory element to second storage nodes within said second dual-port memory element.
8. The memory cell of claim 7 , where said data transfer circuit comprises:
a pair of pass transistors having gate terminals electrically connected to corresponding ones of the first storage nodes and first current carrying terminals electrically connected to corresponding ones of the second storage nodes; and
a pull-down transistor having a current carrying terminal electrically connected to second current carrying terminals of said pair of pass transistors and a gate terminal responsive to the direct path word line signal.