IP Library › Granted Patent US 10,110,209
Granted Patent B1
US 10,110,209 · App. 14/675,369 · Granted Oct 23, 2018

Process compensated delay

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Quick Facts
Patent No.
US 10,110,209
App. No.
14/675,369
Granted
Oct 23, 2018
Kind
B1
Abstract

A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.

Claims (3)

1. An apparatus comprising a positive temperature coefficient bandgap reference coupled to a positive input of an operational amplifier, an output of said operational amplifier coupled to a first transistor gate, a source of said first transistor directly coupled to a negative input of said operational amplifier and a drain of a second transistor, a drain of said first transistor coupled to a current mirror, a thick oxide nMOS varactor coupled to said current mirror.

2. The apparatus of claim 1 wherein said second transistor operates in a triode region.

3. The apparatus of claim 2 wherein said second transistor has a negative temperature coefficient.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2018
From: MAJUMDER, AMIT
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 046884/0923 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →