Method and apparatus for fast PLL initialization

1. A method comprising:

receiving a phase locked loop (PLL) input signal;

receiving a PLL feedback signal, wherein said PLL feedback signal is selected from the group consisting of substantially a voltage controlled oscillator (VCO) output, and substantially said VCO output divided by N wherein N is an integer;

generating a comparison signal based on said received PLL input signal and said received PLL feedback signal;

generating a first control signal based on said comparison signal;

generating a second control signal based upon a prespecified value programmed into a register, wherein said prespecified value is selected from the group consisting of a substantially static value, a value determined at time of manufacture, a value loaded at power up, a value loaded at reset, a value loaded at a frequency change, a value loaded from a nonvolatile memory, a value loaded by a serial control chain, and a value loaded by a parallel control chain;

receiving a selection signal;

selecting either said first control signal or said second control signal based upon said received selection signal;

controlling said VCO (voltage controlled oscillator) by controlling three or more multiplexers based upon said selected control signal, wherein said VCO generates a VCO output, and wherein said three or more multiplexers control how many delay elements are in said VCO.

2. A method for initializing a phase locked loop (PLL) to a frequency comprising:

receiving a PLL clock input signal;

receiving a PLL feedback signal, wherein said PLL feedback signal is selected from the group consisting of substantially a voltage controlled oscillator (VCO) output, and substantially said VCO output divided by N wherein N is an integer;

generating a comparison signal based on said received PLL input signal and said received PLL feedback signal;

generating a first control signal based on said comparison signal;

generating a second control signal based upon a prespecified value programmed into a first register, wherein said prespecified value is selected from the group consisting of a substantially static value, a value determined at time of manufacture, a value loaded at power up, a value loaded at reset, a value loaded at a frequency change, a value loaded from a nonvolatile memory, a value loaded by a serial control chain, and a value loaded by a parallel control chain;

receiving a selection signal;

selecting either said first control signal or said second control signal based upon said received selection signal; and

controlling said frequency by controlling three or more multiplexers in said VCO wherein said controlling is via a second register, wherein said three or more multiplexers control how many delay elements are in said VCO, and wherein said PLL does not need a PLL input.

3. The method of claim 2 wherein said PLL can operate without receiving said PLL clock input signal.

4. An apparatus comprising:

a comparator having a reference signal input, a feedback input, and an output;

a first control circuit having an input and an output, said input in communication with said comparator output;

a second control circuit having an input and an output, said second control circuit input coupled to a first serial register, said second control circuit input capable of receiving communications for adjusting said second control circuit output;

a selection circuit capable of selecting either said first control circuit output or said second control circuit output; and

a controllable oscillator having an input control and an output, said controllable oscillator input control in communication with said selected first control circuit output or said selected second control circuit output via said selection circuit, and said controllable oscillator output in communication with said comparator feedback input, and wherein said controllable oscillator is controlled by three or more multiplexers wherein said controlled is via a second register, wherein said three or more multiplexers control how many delay elements are in said VCO, and wherein said controllable oscillator does not need a frequency input.

5. The apparatus of claim 4 wherein said second control circuit further comprises a digital to analog converter (DAC) wherein said second control circuit output is an output of said DAC.

6. The apparatus of claim 4 wherein said second control circuit further comprises adjusting a number of delay elements in a ring oscillator of said controllable oscillator.

7. The apparatus of claim 4 wherein said second control circuit further comprises adjusting a delay loop of said controllable oscillator.