Memory channel selection control

1. An apparatus comprising:

a first circuit comprising (i) a controller port and (ii) a plurality of memory ports;

a second circuit comprising (i) an input port and (ii) a plurality of output ports; and

a channel decoder configured to (A) decode a selection signal and (B) select (i) one of said plurality of memory ports and (ii) one of said plurality of output ports in response to said decoded selection signal, wherein (i) said selection signal is received by (a) said controller port and said channel decoder in a first mode and (b) said input port and said channel decoder in a second mode, (ii) said first circuit implements a first multiplexer path operating at a first speed, (iii) said second circuit implements a second multiplexer path operating at a second speed and (iv) said first speed is greater than said second speed.

2. The apparatus according to claim 1 , wherein said selection signal is embedded in a command sent to said apparatus by a solid state drive controller.

3. The apparatus according to claim 2 , wherein (i) a plurality of memory modules ignore said selection signal and (ii) decoding said selection signal is implemented to select one memory bank from a plurality of memory banks.

4. The apparatus according to claim 1 , wherein decoding said selection signal bypasses a delay associated with selecting a memory bank based on a signal sent from a general purpose input/output pin of a solid state drive.

5. The apparatus according to claim 1 , wherein (i) said controller port and said plurality of memory ports are each bidirectional and (ii) said input port and said plurality of output ports are each unidirectional.

6. The apparatus according to claim 1 , wherein said first circuit is configured to transmit data signals between a memory controller circuit and a plurality of memory banks.

7. The apparatus according to claim 1 , wherein said second circuit is configured to transmit control signals from a memory controller circuit and a plurality of memory banks.

8. The apparatus according to claim 1 , wherein (i) said controller port and said input port are configured to interface with a controller circuit of a solid state drive and (ii) said memory ports and said output ports are configured to interface with memory banks.

9. The apparatus according to claim 1 , wherein said apparatus implements a first speed/second speed multiplexer pair.

10. The apparatus according to claim 1 , wherein said apparatus implements a memory expander for a solid state drive.

11. The apparatus according to claim 10 , wherein said memory expander is configured to increase an amount of memory banks accessible by a controller circuit.

12. The apparatus according to claim 11 , wherein a number of said memory banks associated with said apparatus is four.

13. The apparatus according to claim 1 , wherein said apparatus comprises four of said memory ports and four of said output ports.

14. The apparatus according to claim 1 , wherein (i) said apparatus is associated with one memory channel and (ii) said memory channel comprises a plurality of memory banks.

15. The apparatus according to claim 14 , wherein (i) a memory circuit comprises a plurality of said memory channels, (ii) a plurality of said apparatuses are implemented and (iii) each of said plurality of said apparatuses are configured to transfer data to/from said plurality of memory banks of an associated one of said memory channels.

16. An apparatus comprising:

a first circuit comprising (i) a controller port and (ii) a plurality of memory ports;

a second circuit comprising (i) an input port and (ii) a plurality of output ports; and

a channel decoder configured to (A) decode a selection signal and (B) select (i) one of said plurality of memory ports and (ii) one of said plurality of output ports in response to said decoded selection signal, wherein (i) said selection signal is received by said controller port and said channel decoder, (ii) said selection signal is transmitted to (a) said first circuit and (b) said channel decoder from a solid state drive controller, (iii) said controller port and said input port are configured to interface with said solid state drive controller and (iv) said memory ports and said output ports are configured to interface with memory banks.

17. The apparatus according to claim 16 , wherein (i) said first circuit implements a first multiplexer path operating at a first speed, (ii) said second circuit implements a second multiplexer path operating at a second speed and (iii) said first speed is greater than said second speed.

18. An apparatus comprising:

a first circuit comprising (i) a controller port and (ii) a plurality of memory ports;

a second circuit comprising (i) an input port and (ii) a plurality of output ports; and

a channel decoder configured to (A) decode a selection signal and (B) select (i) one of said plurality of memory ports and (ii) one of said plurality of output ports in response to said decoded selection signal, wherein (i) said selection signal is received by said input port and said channel decoder, (ii) said selection signal is transmitted to (a) said second circuit and (b) said channel decoder from a solid state drive controller, (iii) said first circuit implements a first multiplexer path operating at a first speed, (iv) said second circuit implements a second multiplexer path operating at a second speed and (v) said first speed is greater than said second speed.