IP Library Granted Patent US 8,289,061
Granted Patent B2
US 8,289,061 · App. 12/569,730 · Granted Oct 16, 2012

Technique to reduce clock recovery amplitude modulation in high-speed serial transceiver

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Quick Facts
Patent No.
US 8,289,061
App. No.
12/569,730
Granted
Oct 16, 2012
Kind
B2
Abstract

A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.

Claims (53)

1. A method of generating a clock signal, comprising,

determining a first amplitude for a first sinusoidal signal;

determining a second amplitude for a second sinusoidal signal that is 90° out of phase from the first sinusoidal signal; and

forming the clock signal by combining the first sinusoidal signal with the second sinusoidal signal;

wherein the first and second amplitudes are quantized values chosen such that an amplitude of a combination of the first sinusoidal signal and the second sinusoidal signal is substantially constant as the first amplitude changes.

2. A method of claim 1 , wherein the method is operated by a computer.

3. A method of claim 1 , the amplitudes of the first sinusoidal signal and second sinusoidal signal are stored as a look up table in a non-transitory computer readable media.

4. A method of claim 1 , further comprising:

providing a phase interpolator having a plurality of reference stage circuits each having a plurality of current source circuits, and using the first and second amplitudes to control the current source circuits, the current source circuits having a predetermined phase offset relative to one another, and coupled via drains of transistors.

5. The method of claim 4 , further comprising:

providing an input terminal to the current sources to receive an input control signal.

6. The method of claim 5 , further comprising:

providing a N-bit digital filter using a look-up table to provide a control input to the input terminal of the current sources.

7. A method of claim 1 , the amplitudes of the first sinusoidal signal and second sinusoidal signal are listed in a look-up table, wherein the look-up table is stored in a non-transitory computer readable media.

8. A method of adjusting a phase interpolator comprising:

determining a first amplitude for a first sinusoidal signal;

determining a second amplitude for a second sinusoidal signal that is 90° out of phase from the first sinusoidal signal; and

forming a clock signal by combining the first sinusoidal signal with the second sinusoidal signal;

wherein the first and second amplitudes are chosen from a lookup table

stored in a non-transitory computer readable media;

further wherein forming the lookup table comprises:

listing a set of quantized values for the first amplitude;

calculating values of an intermediate amplitude from the first amplitude and a first constant; and

assigning a quantized value to the second amplitude from the intermediate amplitude.

9. The method of claim 8 , further comprising:

scaling the amplitude values in the lookup table.

10. The method of claim 8 wherein forming the lookup table further comprises listing a third amplitude using the quantized values of the first amplitude and the quantized values of the second amplitude.

11. The method of claim 10 wherein listing the third amplitude comprises calculating a square root of a sum of the first quantized values squared, and the quantized values of the second amplitude, squared.

12. A method of adjusting a phase interpolator comprising:

determining a first amplitude for a first sinusoidal signal;

determining a second amplitude for a second sinusoidal signal that is 90° out of phase from the first sinusoidal signal; and

forming a clock recovery signal by combining the first sinusoidal signal with the second sinusoidal signal;

wherein the first and second amplitudes are quantized values chosen such that the amplitude of the clock recovery signal is substantially constant as the first amplitude changes, the amplitudes of the first sinusoidal signal and second sinusoidal signal are listed in a look-up table, and the look-up table is stored in a non-transitory computer readable media.

13. A method of adjusting a phase interpolator comprising:

determining a first amplitude for a first sinusoidal signal;

determining a second amplitude for a second sinusoidal signal that is 90° out of phase from the first sinusoidal signal; and

forming a clock recovery signal by combining the first sinusoidal signal with the second sinusoidal signal;

wherein the first and second amplitudes are chosen such that the amplitude of the clock recovery signal is substantially a first constant, the amplitudes of the first sinusoidal signal and second sinusoidal signal are listed in a look-up table, and the look-up table is stored in a non-transitory computer readable media; wherein

the amplitude of the clock recovery signal is obtained by calculating the square root of a sum of the first amplitude's square and the second amplitude's square; and assigning the square root value to the amplitude of the clock recovery signal.

14. The method of claim 13 wherein the phase of the clock recovery signal is obtained from the ratio of the second amplitude to the first amplitude.

15. A method of adjusting a phase interpolator comprising:

determining a first amplitude for a first sinusoidal signal;

determining a second amplitude for a second sinusoidal signal that is 90° out of phase from the first sinusoidal signal; and

forming a clock recovery signal by combining the first sinusoidal signal with the second sinusoidal signal;

wherein the first and second amplitudes are quantized values chosen from a look-up table, and the look-up table is stored in a non-transitory computer readable media; wherein

the lookup table is formed by:

listing a set of values for the first amplitude in the look-up table;

calculating values of an intermediate amplitude from the first amplitude and the first constant;

quantizing the values of the intermediate amplitude;

assigning the quantized values to the second amplitude in the look-up table.

16. The method of claim 15 wherein the set of values for the first amplitude is a list of 2 N integers greater than 0 and smaller than 2 N , where N is the preferred bit number of a digital processor coupled to the phase interpolator.

17. The method of claim 15 wherein quantizing the values of the intermediate amplitude comprises finding an integer number such that the square root of the sum of the first amplitude squared and the second amplitude squared is a number greater than 2 N -1 and no greater than 2 N .

18. The method of claim 17 wherein every pair of first amplitude and second amplitude in the lookup table is different

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →