IP Library Granted Patent US 8,324,948
Granted Patent B1
US 8,324,948 · App. 12/889,254 · Granted Dec 4, 2012

Method and apparatus for duty-cycle correction with reduced current consumption

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Quick Facts
Patent No.
US 8,324,948
App. No.
12/889,254
Granted
Dec 4, 2012
Kind
B1
Abstract

A method and apparatus for duty-cycle correction with reduced current consumption have been described.

Claims (33)

1. A method for duty cycle correction comprising:

receiving an output signal;

phase splitting said output signal producing phase split signals;

applying said phase split signals to a resistor-capacitor network; and

using two outputs from said resistor-capacitor network to duty cycle correct said output signal.

2. The method of claim 1 wherein said resistor-capacitor network further comprises a first transmission gate and a second transmission gate.

3. The method of claim 2 wherein said first transmission gate has an input coupled to said resistor-capacitor network and an output coupled to a correction circuit input.

4. The method of claim 3 wherein said second transmission gate has an input coupled to reference voltage and an output coupled to said correction circuit input.

5. The method of claim 4 wherein said second transmission gate when activated sets said correction circuit input to said reference voltage.

6. The method of claim 5 further comprising a switch which when activated sets said two outputs from said resistor-capacitor network to a same voltage.

7. An apparatus comprising:

a duty cycle correction circuit having an output, a first duty cycle correction input, and a second duty cycle correction input;

a phase splitter having an input, a first output, and a second output, said phase splitter input coupled to said duty cycle correction circuit output;

a first resistor-capacitor network having an input and an output, said first resistor-capacitor network input coupled to said phase splitter first output; and

a second resistor-capacitor network having an input and an output, said second resistor-capacitor network input coupled to said phase splitter second output.

8. The apparatus of claim 7 further comprising:

a first transmission gate having an input and an output, said first transmission gate input coupled to said first resistor-capacitor network output; and

a second transmission gate having an input and an output, said second transmission gate input coupled to said second resistor-capacitor network output.

9. The apparatus of claim 8 further comprising:

a switch between said first transmission gate output and said second transmission gate output.

10. The apparatus of claim 9 further comprising:

wherein said first transmission gate output is coupled to said first duty cycle correction input.

11. The apparatus of claim 10 further comprising:

wherein said second transmission gate output is coupled to said second duty cycle correction input.

12. The apparatus of claim 11 further comprising:

a third transmission gate having an input and an output, said third transmission gate output coupled to said first transmission gate output; and

a fourth transmission gate having an input and an output, said fourth transmission gate output coupled to said second transmission gate output.

13. The apparatus of claim 12 further comprising:

wherein said third transmission gate input and said fourth transmission gate input are coupled to a reference voltage.

14. A method comprising;

phase splitting a signal to be duty cycle corrected thereby producing a plurality of outputs;

averaging each of said plurality of outputs;

using said averaged each plurality of outputs to duty cycle correct said signal; and setting said plurality of outputs to a reference voltage before beginning said averaging said plurality of outputs.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2010
From: MAJUMDER, AMIT
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 025088/0985 →