IP Library Granted Patent US 8,350,743
Granted Patent B2
US 8,350,743 · App. 13/085,748 · Granted Jan 8, 2013

AD converter

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,350,743
App. No.
13/085,748
Granted
Jan 8, 2013
Kind
B2
Abstract

Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second switch. These switches from both outputs of the differential amplifier to the same circuit node of the AD conversion circuit are both made conductive simultaneously prior to making the selected one of the first and second switch conductive. In this way, the amplifier output voltage is reset without requiring a dedicated switch just for this purpose.

Claims (17)

1. An electronic circuit comprising

a sample and hold circuit having a differential amplifier with a first and a second output for a differential amplifier output voltage between the first and second output;

an analog to digital converter;

a first and a second switch coupled between a circuit node of the analog to digital converter and the first and second outputs of the differential amplifier respectively,

a control circuit having outputs coupled to control inputs of the first and second switches, the control circuit being configured to generate control signals at the control inputs of the first and second switches that define a short circuit phase, a transfer phase and a passive phase, making the first and second switches simultaneously conductive in the short circuit phase, making a selectable one of the first and second switches conductive and the other non-conductive in the transfer phase and making both the first and second switches non-conductive in the passive phase.

2. An electronic circuit according to claim 1 , further comprising a further analog to digital converter, a third and a fourth switch coupled between a circuit node of the further analog to digital converter and the first and second outputs of the amplifier respectively, the control circuit being configured to generate control signals at control inputs of the third and fourth switches alternately defining a first succession of a short circuit phase and a transfer phase for the first and second switches while applying a passive phase to the third and fourth switches and a second succession of a short circuit phase and a transfer phase for the third and fourth switches while applying a passive phase to the first and second switches.

3. An electronic circuit according to claim 1 , wherein the analog to digital converter has differential circuit nodes, including said circuit node and a further circuit node for receiving a differential signal between the circuit node and the further circuit node, the electronic circuit having a first group of switches, including a first and a second pair of switches, the first and second pairs including said first and second switches respectively, and a further first and second switches coupled between the further circuit node of the analog to digital converter and the second and first outputs of the differential amplifier respectively, the control circuit being configured to make the switches in the first pair conductive and non conductive together and to make the switches in the second pair conductive and non conductive together.

4. An electronic circuit according to claim 1 , wherein the sample and hold circuit includes feedback switches coupled between the outputs of the differential amplifier and its inputs, the control circuit having outputs coupled to inputs of the feedback switches, the control circuit being configured to apply the short circuit phase while making the feedback switches non-conductive.

5. An electronic circuit according to claim 1 , wherein no switch is directly connected from the first output of the differential amplifier to the second outputs of the differential amplifier.

6. A method of performing analog to digital conversion comprising

sampling an input voltage;

generating a differential amplifier output voltage between a first and a second output of a differential amplifier in response to the sampled input voltage;

selecting a conversion polarity;

making a first switch from the first output of the differential amplifier or a second switch from the second output of the differential amplifier to a circuit node of an analog to digital conversion circuit conductive dependent on the selected conversion polarity; and

making both the first and second switches conductive simultaneously, prior to making the selected one of the first and second switches conductive.

7. A method according to claim 6 , further comprising making selected ones of the first and second switches between circuit nodes of a first and a second analog to digital conversion circuit and the first and second outputs of the differential amplifier conductive, alternately for the first and second analog to digital conversion circuits and, when making the selected one of the first and second switches to the circuit node conductive making of the first or second analog to digital conversion circuits conductive, making both the first and second switches to the circuit node conductive before making the selected one of the first and second switches to that circuit node conductive.

8. A method according to claim 6 , wherein, when the first and output of the differential amplifier are short circuited to each other, they are always short circuited entirely via one or more switches to one or more circuit nodes of the analog to digital conversion circuit, or one or more circuit nodes of one or more other analog to digital conversion circuits that are operated in parallel to the analog to digital conversion circuit.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2012
From: NXP B.V.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 029213/0890 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2011
From: VAN DE VEL, HANS; BUTER, BERRY ANTHONY JOHANNUS
To: NXP B.V.
Reel/Frame 026121/0370 →