Reducing charge imbalance in a charge pump of a phase locked loop (PLL) through maintaining an output node thereof at a same voltage as a bypass node thereof
View Patent ↗A method includes providing an active circuit element in a feedback path between an output node and a bypass node of a charge pump of a Phase Locked Loop (PLL). The bypass node is a node to which a charge current or a discharge current is steered to by the charge pump when neither charging the output node nor discharging the output node is required. The method also includes servoing the bypass node to the output node through the active circuit element in the feedback path to maintain a same voltage at the output node and the bypass node when neither the charging of the output node nor the discharging of the output node is required.
1. A method comprising:
providing an active circuit element in a feedback path between an output node and a bypass node of a charge pump of a Phase Locked Loop (PLL), the bypass node being a node to which one of a charge current and a discharge current is steered to by the charge pump when neither charging the output node nor discharging the output node is required; and
servoing the bypass node to the output node through the active circuit element in the feedback path to maintain a same voltage at the output node and the bypass node when neither the charging of the output node nor the discharging of the output node is required.
2. The method of claim 1 , comprising providing an operational amplifier as the active circuit element in the feedback path, the operational amplifier being configured to receive a voltage from the output node and a voltage from the bypass node as inputs thereto.
3. The method of claim 1 , comprising providing a pair of transistors in a path comprising the bypass node, the bypass node being taken from a path coupling a transistor of the pair to another transistor thereof.
4. The method of claim 1 , further comprising:
providing a first transistor configured to function as a switch in a path enabling the charging of the output node;
providing a second transistor also configured to function as a switch in a path enabling the discharging of the output node; and
controlling the charging and the discharging of the output node based on an output of a phase detector of the PLL.
5. The method of claim 4 , wherein the first transistor and the second transistor are Metal-Oxide-Semiconductor (MOS) transistors configured to have a voltage associated with the output of the phase detector applied to gate terminals thereof.
6. The method of claim 3 , wherein the pair of transistors in the path comprising the bypass node includes a MOS transistor pair.
7. The method of claim 4 , further comprising:
providing the active circuit element in each of a feedback path between the output node and the bypass node associated with the first transistor and a feedback path between the output node and the bypass node associated with the second transistor;
coupling a current source associated with the first transistor to a first supply voltage; and
coupling another current source associated with the second transistor to a second supply voltage less than the first supply voltage, the second supply voltage also capable of being a ground voltage.
8. A PLL comprising:
a phase detector configured to generate an output; and
a charge pump configured to be controlled by the output of the phase detector, the charge pump comprising an active circuit element in a feedback path between an output node and a bypass node thereof, the bypass node being a node to which one of a charge current and a discharge current is steered to by the charge pump when neither charging the output node nor discharging the output node is required,
wherein the bypass node is servoed to the output node through the active circuit element in the feedback path to maintain a same voltage at the output node and the bypass node when neither the charging of the output node nor the discharging of the output node is required.
9. The PLL of claim 8 , wherein the active circuit element in the feedback path between the output node and the bypass node of the charge pump is an operational amplifier configured to receive a voltage from the output node and a voltage from the bypass node as inputs thereto.
10. The PLL of claim 8 , wherein a path comprising the bypass node of the charge pump includes a pair of transistors, the bypass node being taken from a path coupling a transistor of the pair to another transistor thereof.
11. The PLL of claim 8 , wherein the charge pump further comprises:
a first transistor configured to function as a switch in a path enabling the charging of the output node; and
a second transistor also configured to function as a switch in a path enabling the discharging of the output node,
wherein the charging and the discharging of the output node are configured to be controlled based on the output of the phase detector.
12. The PLL of claim 11 , wherein the first transistor and the second transistor of the charge pump are MOS transistors configured to have a voltage associated with the output of the phase detector applied to gate terminals thereof.
13. The PLL of claim 10 , wherein the pair of transistors in the path comprising the bypass node of the charge pump includes a MOS transistor pair.
14. The PLL of claim 11 ,
wherein the active circuit element is provided in each of a feedback path between the output node and the bypass node associated with the first transistor of the charge pump and a feedback path between the output node and the bypass node associated with the second transistor of the charge pump, and
wherein the charge pump further comprises a current source associated with the first transistor coupled to a first supply voltage and another current source associated with the second transistor coupled to a second supply voltage less than the first supply voltage, the second supply voltage also capable of being a ground voltage.
15. A receiver comprising:
a mixer configured to mix an input signal with a Local Oscillator (LO) signal to an Intermediate Frequency (IF); and
an LO generation circuit configured to generate the LO signal, the LO generation circuit including a PLL therein, the PLL comprising:
a phase detector configured to generate an output; and
a charge pump configured to be controlled by the output of the phase detector, the charge pump comprising an active circuit element in a feedback path between an output node and a bypass node thereof, the bypass node being a node to which one of a charge current and a discharge current is steered to by the charge pump when neither charging the output node nor discharging the output node is required,
wherein the bypass node is servoed to the output node through the active circuit element in the feedback path to maintain a same voltage at the output node and the bypass node when neither the charging of the output node nor the discharging of the output node is required.
16. The receiver of claim 15 , wherein the active circuit element in the feedback path between the output node and the bypass node of the charge pump is an operational amplifier configured to receive a voltage from the output node and a voltage from the bypass node as inputs thereto.
17. The receiver of claim 15 , wherein a path comprising the bypass node of the charge pump includes a pair of transistors, the bypass node being taken from a path coupling a transistor of the pair to another transistor thereof.
18. The receiver of claim 15 , wherein the charge pump further comprises:
a first transistor configured to function as a switch in a path enabling the charging of the output node; and
a second transistor also configured to function as a switch in a path enabling the discharging of the output node,
wherein the charging and the discharging of the output node are configured to be controlled based on the output of the phase detector.
19. The receiver of claim 18 , wherein the first transistor and the second transistor of the charge pump are MOS transistors configured to have a voltage associated with the output of the phase detector applied to gate terminals thereof.
20. The receiver of claim 17 , wherein the pair of transistors in the path comprising the bypass node of the charge pump includes a MOS transistor pair.