IP Library Granted Patent US 9,264,027
Granted Patent B1
US 9,264,027 · App. 14/190,890 · Granted Feb 16, 2016

Process compensated delay

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Quick Facts
Patent No.
US 9,264,027
App. No.
14/190,890
Granted
Feb 16, 2016
Kind
B1
Abstract

A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.

Claims (9)

1. A method comprising using a varactor and generating a delay based primarily on electron mobility, wherein said using a varactor is using a varactor fabricated on an integrated circuit, wherein said generating a delay further comprises utilizing a current source said current source directly coupled to said varactor fabricated on said integrated circuit, wherein said current source is fabricated on said integrated circuit, and further comprising shunting directly across said varactor on said integrated circuit using a transistor.

2. The method of claim 1 wherein said transistor is an nMOS device.

3. An integrated circuit apparatus comprising a bandgap reference coupled to a current source which is in operative communication with a varactor to produce a delay dependent primarily on an electron mobility of said integrated circuit wherein said bandgap reference has a positive temperature coefficient wherein said bandgap reference coupled to said current source further comprises coupling said band reference to a scaling circuit input, coupling an output of said scaling circuit to said current source, and wherein said current source is directly coupled to a shunting transistor and wherein said current source is directly coupled to said varactor.

4. An integrated circuit apparatus comprising a bandgap reference coupled to a current source which is in operative communication with a varactor to produce a delay dependent primarily on an electron mobility of said integrated circuit wherein said bandgap reference has a positive temperature coefficient wherein said bandgap reference coupled to said current source further comprises coupling said band reference to a scaling circuit input, coupling an output of said scaling circuit to said current source, wherein said current source is a current mirror, and wherein said current source is directly coupled to a shunting transistor and wherein said current source is directly coupled to said varactor.

5. An integrated circuit apparatus comprising a bandgap reference coupled to a current source which is in operative communication with a varactor to produce a delay dependent primarily on an electron mobility of said integrated circuit, wherein said bandgap reference has a positive temperature coefficient, wherein said current source has a negative temperature coefficient, wherein said current source is directly coupled to a shunting transistor and wherein said current source is directly coupled to said varactor.

6. The integrated circuit apparatus of claim 5 wherein said current source is directly coupled to a shunting transistor and wherein said current source is directly coupled to said varactor.

7. An apparatus comprising a positive temperature coefficient bandgap reference coupled to a positive input of an operational amplifier, an output of said operational amplifier coupled to a first transistor gate, a source of said first transistor directly coupled to a negative input of said operational amplifier and a drain of a second transistor, a drain of said first transistor coupled to a current mirror, a third transistor coupled to said current mirror and a gate of said third transistor coupled to an enable block.

8. The apparatus of claim 7 wherein said second transistor operates in a triode region.

9. The apparatus of claim 8 wherein said second transistor has a negative temperature coefficient.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2018
From: MAJUMDER, AMIT
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 046884/0923 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →