Phase step clock generator
View Patent ↗An integrated circuit includes a phase step generator and a clock circuit. The phase step generator generates an input clock signal based on a reference clock and the clock circuit generates an output clock signal based on the input clock signal. Additionally, the clock circuit generates a feedback clock signal based on the output clock signal and locks a phase of the feedback clock signal with a phase of the input clock signal. In response to an assertion of a trigger signal, the phase step generator extends a phase of the input clock signal by inserting a phase step into the reference clock signal. A bandwidth of the clock circuit is determined based on the output clock signal after assertion of the trigger signal.
1. A method of determining a bandwidth of a clock circuit embedded in an integrated circuit, the method comprising:
generating an input clock signal based on a reference clock signal;
extending a phase of the input clock signal by inserting a phase step into the reference clock signal in response to a trigger signal;
generating an output clock signal based on the input clock signal; and
determining a bandwidth of the clock circuit based on the output clock signal by measuring phase differences between the reference clock signal and the output clock signal, constructing a step response based on the measured phased differences and determining the bandwidth of the clock circuit based on the step response.
2. The method of claim 1 , wherein the phase step has a duration of a half cycle in the reference clock signal.
3. The method of claim 1 , wherein determining the bandwidth of the clock circuit based on the step response comprises performing Fourier analysis on the step response.
4. A method of determining a bandwidth of a clock circuit embedded in an integrated circuit, the method comprising:
generating an input clock signal based on a reference clock signal;
extending a phase of the input clock signal by inserting a phase step into the reference clock signal in response to a trigger signal;
generating an output clock signal based on the input clock signal; and
generating a lock signal based on the output clock signal;
determining the bandwidth of the clock circuit based on the output clock signal and based on the lock signal.
5. A method of determining a bandwidth of a clock circuit embedded in an integrated circuit, the method comprising:
generating an input clock signal based on a reference clock signal;
extending a phase of the input clock signal by inserting a phase step into the reference clock signal in response to a trigger signal, the extending a phase of the input clock signal comprising generating a synchronized trigger signal by synchronizing the trigger signal with the reference clock signal, generating an inverted trigger signal based on the synchronized trigger signal, generating a delayed trigger signal based on the synchronized trigger signal and the reference clock signal, generating a filter signal based on the inverted trigger signal and the delayed trigger signal, generating an inverted reference clock signal by inverting the reference clock signal, generating an offset trigger signal based on the synchronized trigger signal and the inverted reference clock signal, generating a phase-extended signal by selecting the reference clock signal or the inverted reference clock signal based on the offset trigger signal and filtering the phase-extended signal based on the filter signal;
generating an output clock signal based on the input clock signal; and
determining a bandwidth of the clock circuit based on the output clock signal.