Input termination circuitry with high impedance at power off

1. An input termination circuit for terminating transmission lines of a communication system, comprising:

a first and a second resistor, each having a terminal respectively coupled to a first and second input terminal of the input termination circuit;

a first and a second transistor coupled in series between the first resistor and the second resistor, the gates of the first and the second transistor being coupled to a control circuit; and

a third transistor having two terminals respectively coupled to the control circuit and a node between the first and the second transistor, wherein the gate of the third transistor is coupled to ground.

2. The input termination circuit according to claim 1 , wherein the first and the second transistor are CMOS transistors.

3. The input termination circuit according to claim 1 , wherein the third transistor is a CMOS transistor.

4. The input termination circuit according to claim 1 , wherein the first and the second transistor are NMOS transistors.

5. The input termination circuit according to claim 1 , wherein the first and the second transistor are PMOS transistors.

6. The input termination circuit according to claim 1 , wherein the control circuit is configured to provide a control voltage to the gates of the first and the second transistor when the control circuit is powered on.

7. The input termination circuit according to claim 6 , wherein the control circuit includes a PMOS transistor and an NMOS transistor coupled in series between a power supply and ground.

8. The input termination circuit according to claim 1 further comprising a buffer circuit configured to provide a reference voltage at the node between the first and the second transistor.

9. The input termination circuit according to claim 8 , wherein the buffer circuit includes a PMOS transistor and an NMOS transistor coupled in series between a power supply and ground.

10. The input termination circuit according to claim 1 , wherein the first and the second resistor each have a resistance value of about half of a termination resistance that matches characteristic impedance of transmission lines, which the input termination circuit is adapted to be coupled to.

11. The input termination circuit according to claim 1 , wherein the first and the second resistor have resistance value of about half of a termination resistance, which is selected from a group consisting of 75 Ohm, 100 Ohm, 110 Ohm, and 120 Ohm.

12. The input termination circuit according to claim 1 , wherein the resistance of the first and the second resistor is programmable.

13. The input termination circuit according to claim 1 further comprising a third and a fourth resistor respectively coupled to a first and a second input terminal of the input termination circuit, wherein the third and the fourth resistor each have an impedance value of about and over 500 Ohm.

14. The input termination circuit according to claim 1 further comprising two electrostatic discharge (ESD) protection circuits respectively coupled to the first and the second input terminal of the input termination circuit.

15. An input termination circuit for terminating transmission lines of a communication system, comprising:

a first and a second input terminal adapted to be coupled to the transmission lines;

a control circuit configured to provide a control voltage at a node of the control circuit;

a first and a second resistor each having a terminal respectively coupled to the first and the second input terminal;

a first and a second transistor coupled in series between the first resistor and the second resistor, the gates of the two transistors being coupled to the node for providing the control voltage; and

a third transistor having two terminals respectively coupled to the node for providing the control voltage of the control circuit and a node between the first and the second transistor, wherein the gate of the third transistor is coupled to ground.

16. The input termination circuit according to claim 1 further comprising a buffer circuit configured to provide a reference voltage at the node between the first and the second transistor.

17. The input termination circuit according to claim 16 , wherein the buffer circuit includes a PMOS transistor and an NMOS transistor coupled in series between a power supply and ground.

18. The input termination circuit according to claim 15 , wherein the control circuit includes a PMOS transistor and an NMOS transistor coupled in series between a power supply and ground.

19. The input termination circuit according to claim 15 , wherein the first and the second resistor each have a resistance value of about half of a termination resistance that matches the characteristic impedance of transmission lines, which the input termination circuit is adapted to be coupled to.

20. The input termination circuit according to claim 15 , wherein the first and the second resistor each have a resistance value of about half of a termination resistance, which is selected from a group consisting of 75 Ohm, 100 Ohm, 110 Ohm, and 120 Ohm.

21. The input termination circuit according to claim 15 , wherein the resistance of the first and the second resistor is programmable.

22. The input termination circuit according to claim 15 further comprising a third and a fourth resistor respectively coupled to the first and the second input terminal of the input termination circuit, wherein the third and the fourth resistor each have a resistance value of about 500 Ohm.

23. The input termination circuit according to claim 15 further comprising two electrostatic discharge (ESD) protection circuits respectively coupled to the first and the second input terminal of the input termination circuit.