Method for reliable injection of deterministic jitter for high speed transceiver simulation
View Patent ↗A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measuring the time the clock and data recovery system takes to achieve bit lock of a phase modulated signal. Data uncorrelated timing jitter corresponding to a user defined probability distribution is included in the jitter testing signal. Utilization of a variable probability distribution in generating data uncorrelated timing jitter, as provided by the present invention, allows for greater flexibility and accuracy in clock and data recovery circuit testing and characterization.
1. A method of testing a clock and data recovery circuit, the method comprising:
generating a jitter signal including data-uncorrelated jitter having a defined probability distribution;
generating a jitter-free data signal;
phase modulating the jitter-free data signal by the jitter signal to generate a phase modulated signal; and
measuring a bit lock acquisition time of the clock and data recovery circuit to achieve bit lock of the phase modulated signal.
2. The method of claim 1 , wherein said jitter signal further includes random jitter.
3. The method of claim 2 , wherein said random jitter has specified standard deviation and mean values.
4. The method of claim 2 , wherein said random jitter has a Gaussian probability distribution.
5. The method of claim 1 , wherein said jitter signal further includes sinusoidal jitter.
6. The method of claim 5 , wherein said sinusoidal jitter has specified frequency ranges.
7. The method of claim 1 , wherein the defined probability distribution is a uniform probability distribution.
8. The method of claim 1 , wherein the jitter-free data signal is a data signal having periodic data patterns.
9. A system for testing a clock and data recovery (CDR) circuit, the system comprising:
a data signal generator configured to generate a jitter-free data signal;
one or more noise signal generators configured to generate a jitter data signal;
a phase modulator in communication with the data signal generator, the CDR circuit and the one or more noise signal generators;
a test signal output from the CDR circuit;
a test signal input to the CDR circuit; and
a detector system in communication with the data signal generator and the CDR circuit, configured to measure a bit lock acquisition time of the CDR circuit by using the jitter-free data signal and the test signal output;
wherein one of the noise signal generator generates data-uncorrelated jitter having a defined probability distribution, and
wherein the phase modulator modulates the jitter-free data signal by the jitter data signal to generate the test signal input.
10. The system of claim 9 , wherein one of the noise signal generators is a sinusoidal signal generator.
11. The system of claim 9 , wherein one of the noise signal generators is a Gaussian noise generator.