Packet processors having multi-functional range match cells therein

1. An integrated circuit device, comprising:

a multi-functional match cell responsive to first and second n-bit operands, said multi-functional match cell configured so that said match cell operates as an n-bit range match cell when the first and second n-bit operands are equivalent, as an n-bit NOR-type CAM cell when the second n-bit operand is masked and as an n-bit NAND-type CAM cell when the first n-bit operand is masked, where “n” is a positive integer greater than one.

2. The integrated circuit device of claim 1 , wherein the multi-functional match cell comprises:

an upper bound comparison circuit responsive to an upper bound or its complement; and

a lower bound comparison circuit responsive to a lower bound or its complement.

3. The integrated circuit device of claim 2 , wherein the first n-bit operand is an n-bit differential signal D and /D and the second n-bit operand is an n-bit differential signal D′ and /D′; and wherein said upper bound comparison circuit is responsive to /D and /D′(or D and D′) and said lower bound comparison circuit is responsive to D and D′ (or /D and /D′).

4. The integrated circuit device of claim 3 , wherein the second n-bit operand is masked by setting D′ and /D′to all 1s.

5. The integrated circuit device of claim 4 , wherein the first n-bit operand is masked by setting D and /D to all 0s.

6. An integrated circuit device, comprising:

a multi-functional match cell responsive to first and second n-bit operands, said multi-functional match cell configured so that said match cell operates as an n-bit range match cell when the first and second n-bit operands are equivalent, as an n-bit NOR-type CAM cell when the second n-bit operand is masked and as an n-bit NAND-type CAM cell when the first n-bit operand is masked, where “n” is a positive integer greater than one, said multi-functional match cell comprising:

an upper bound comparison circuit responsive to an upper bound or its complement; and

a lower bound comparison circuit responsive to a lower bound or its complement;

wherein the first n-bit operand is an n-bit differential signal D and /D and the second n-bit operand is an n-bit differential signal D′ and /D′;

wherein said upper bound comparison circuit is responsive to /D and /D′(or D and D′) and said lower bound comparison circuit is responsive to D and D′ (or /D and /D′): and

wherein said upper bound comparison circuit is configured to evaluate whether the first n-bit operand D[n−1, . . . , 0] applied thereto is “≦” or “>” the upper bound H[n−1, . . . , 0] in accordance with the following upper bound relationship or its boolean or complementary equivalents:

GTO =((( GTI ( D 0 + H 0 )+ D 0 H 0 )( D 1 + H 1 )+ D 1 H 1 )( D 2 + H 2 )+ D 2 H 2 )( D 3 + H 3 )+ D 3 H 3 ,

where GTI is an upper bound control input signal and GTO is an upper bound control output signal.

7. The integrated circuit device of claim 6 , wherein said lower bound comparison circuit is configured to evaluate whether the first n-bit operand D[n−1, . . . , 0] applied thereto is “<” or “≧” the lower bound L[n−1, . . . , 0] in accordance with the following lower bound relationship or its boolean or complementary equivalents:

LTO =( . . . (( LTI ( D 0 + L 0 )+ D 0 L 0 )( D 1 + L 1 )+ D 1 L 1 ) . . . ( D n−2 + L n−2 )+ D n−2 L n−2 )( D n−1 + L n−1 )+ D n−1 L n−1 ,

where LTI is a lower bound control input signal and LTO is a lower bound control output signal.

8. An integrated circuit device, comprising:

a range match circuit configured to evaluate whether an operand D[n−1, . . . , 0] applied thereto is within a range between an upper bound H[n−1, . . . , 0] and a lower bound L[n−1, . . . , 0], in accordance with the following upper bound and lower bound relationships or their boolean or complementary equivalents:

GTO =( . . . (( GTI ( D 0 + H 0 )+ D 0 H 0 )( D 1 + H 1 )+ D 1 H 1 ) . . . ( D n−2 + H n−2 )+ D n−2 H n−2 )( D n−1 + H n−1 )+ D n−1 H n−1 , and

LTO =( . . . (( LTI ( D 0 + L 0 )+ D 0 L 0 )( D 1 + L 1 )+ D 1 L 1 ) . . . ( D n−2 + L n−2 )+ D n−2 L n−2 )( D n−1 + L n−1 )+ D n−1 L n−1 ,

where LTI and /GTI are control input signals and LTO and /GTO are control output signals.

9. A range match circuit, comprising:

an n-bit range match cell responsive to upper and lower bound control input signals and a multi-bit operand, said match cell configured to generate an upper bound control output signal that encodes a “>” inequality between the multi-bit operand and an upper bound operand and a “<” inequality between the multi-bit operand and a lower bound operand when the upper bound control signal is in a first logic state and the lower bound control signal is in a second logic state opposite the first logic state, where “n” is a positive integer greater than one.