Self-adaptive multi-modulus dividers containing div2/3 cells therein
Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P<n:0> during an update time interval and may even fully turn off one or more of the div2/3 cells not participating in a divide-by-N operation, where N is a positive integer greater than one. The div2/3 cells are configured to include a modulus input terminal and a modulus output terminal and the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.
1. An integrated circuit device, comprising:
a multi-modulus divider comprising a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte during an update time interval and freezes one or more of the div2/3 cells not participating in a divide-by-N operation in a power saving mode of operation, where N is a positive integer greater than one; each of a plurality of the div2/3 cells in the cascaded chain has a first terminal responsive to a respective bit of the chain length control byte and a second terminal responsive to a respective bit of a multi-bit stage number control (SNC) byte; and each of a plurality of bits of the SNC byte is derived exclusively from a respective Boolean combination of a plurality of bits of the chain length control byte.
2. The device of claim 1 , wherein each of the div2/3 cells includes a modulus input terminal and a modulus output terminal; and wherein each of the div2/3 cells is configured so that the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.
3. The device of claim 2 , wherein a modulus input terminal of each of a plurality of the div2/3 cells is directly connected to a modulus output terminal of another one of the plurality of div2/3 cells.
4. The device of claim 1 , wherein each of the plurality of bits of the SNC byte is derived from a respective Boolean combination of a different number of bits of the chain length control byte.
5. The device of claim 1 , wherein at least one of the Boolean combinations of a plurality of bits of the chain length control byte includes a logical OR combination of two bits of the chain length control byte.
6. An integrated circuit device, comprising:
a multi-modulus divider comprising a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte during an update time interval and freezes one or more of the div2/3 cells not participating in a divide-by-N operation in a power saving mode of operation, where N is a positive integer greater than one, said cascaded chain comprising a plurality of div2/3 cells having respective stage number control (SNC) terminals that receive respective SNC signals, which are each derived exclusively from respective Boolean combinations of a plurality of bits of the chain length control byte.
7. The device of claim 6 , wherein each of the div2/3 cells includes a modulus input terminal and a modulus output terminal; and wherein each of the div2/3 cells is configured so that the chain length control operation is independent of the magnitude of the signals provided to the modulus input terminals of the div2/3 cells.
8. The device of claim 7 , wherein a modulus input terminal of each of a plurality of the div2/3 cells is directly connected to a modulus output terminal of another one of the plurality of div2/3 cells.
9. The device of claim 8 , wherein said multi-modulus divider is configured so that all switching components within the div2/3 cells in said cascaded chain that do not participate in division in response to the chain length control byte remain static in a power saving mode of operation.
10. The device of claim 6 , wherein said multi-modulus divider is configured so that all switching components within the div2/3 cells in said cascaded chain that do not participate in division in response to the chain length control byte remain static in a power saving mode of operation.
11. An integrated circuit device, comprising:
a multi-modulus divider comprising a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of any intermediate divisor in response to a change in value of a chain length control byte during an update time interval when all modulus input signals (MODin) associated with active ones of the div2/3 cells participating in a divide-by-N operation are in a first logic state, where N is a positive integer greater than one; each of a plurality of the div2/3 cells in the cascaded chain has a first terminal responsive to a respective bit of the chain length control byte and a second terminal responsive to a respective bit of a multi-bit stage number control (SNC) byte; and each of a plurality of bits of the SNC byte is derived exclusively from a respective Boolean combination of a plurality of bits of the chain length control byte.
12. The device of claim 11 , wherein during the update time interval all MODin signals associated with inactive ones of the div2/3 cells not participating in the divide-by-N operation are held in a second logic state, opposite the first logic state.
13. The device of claim 1 , wherein a first one of the Boolean combinations of a plurality of bits of the chain length control byte includes a logical OR combination of only two bits of the chain length control byte; and wherein a second one of the Boolean combinations of a plurality of bits of the chain length control byte includes a logical OR combination of only three bits of the chain length control byte.
14. The device of claim 1 , wherein each of the plurality of div2/3 cells in the cascaded chain comprises circuitry configured to perform a logical AND operation on signals received at the respective first and second terminals thereof.
15. The device of claim 14 , wherein the circuitry includes an output terminal electrically connected to a program node (PGMk) of the first one of the div2/3 cells.
16. The device of claim 14 , wherein the circuitry performs a 2-input logic AND operation.
17. The device of claim 1 , wherein the chain length control byte is a multi-bit signal defined as: P<n:0>, where n is an integer greater than 3; wherein a first terminal of a first of the div2/3 cells in the cascaded chain is responsive to P<0>; and wherein a second terminal of the first of the div2/3 cells in the cascaded chain is responsive to a bit of the SNC byte having a logic value equal to: P<1> OR P<2> OR . . . P<n−1> OR P<n>, where OR designates a logical OR operation.
18. The device of claim 11 , wherein the chain length control byte is a multi-bit signal defined as: P<n:0>, where n is an integer greater than 3; wherein a first terminal of a first of the div2/3 cells in the cascaded chain is responsive to P<0>; and wherein a second terminal of the first of the div2/3 cells in the cascaded chain is responsive to a bit of the SNC byte having a logic value equal to: P<1> OR P<2> OR . . . P<n−1> OR P<n>, where OR designates a logical OR operation.