IP Library Granted Patent US 8,094,770
Granted Patent B2
US 8,094,770 · App. 12/845,434 · Granted Jan 10, 2012

Dynamic phase tracking using edge detection that employs an edge counter

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,094,770
App. No.
12/845,434
Granted
Jan 10, 2012
Kind
B2
Abstract

A phase-locked loop includes a sample selector configured to select a set of samples from an oversampled portion of a data signal, a dynamic phase decision control circuit configured to indicate whether a predetermined number of edges is present in the set of samples, and a phase detector configured to determine a skew condition and a direction of the skew condition of the set of samples based on the indication of the dynamic phase decision control circuit. The phase detector is configured to produce a set of skew detection signals based on at least one skew condition determination. The phase-locked loop further includes a loop filter configured to filter the set of skew detection signals. The loop filter is also configured to produce a set of phase adjustment signals based on the set of skew detection signals. The sample selector is configured to select a set of samples from the oversampled portion of the data signal, based on the set of phase adjustment signals. In one embodiment, the dynamic phase decision control circuit is also configured to detect an absence of edges in the set of samples, and a state change of the loop filter is inhibited according to the indication of the absence of edges.

Claims (12)

1. A phase-locked loop comprising:

(a) a sample selector configured to select a set of samples from an oversampled portion of a data signal;

(b) a dynamic phase decision control circuit configured to indicate whether a predetermined number of edges is present in the set of samples; and

(c) a phase detector configured to determine a skew condition and a direction of the skew condition of the set of samples based on the indication of the dynamic phase decision control circuit,

wherein said phase detector is configured to produce a set of skew detection signals based on at least one skew condition determination, and wherein said phase-locked loop further comprises a loop filter configured to filter the set of skew detection signals, and

wherein said loop filter is also configured to produce a set of phase adjustment signals based on the set of skew detection signals, and wherein said sample selector is configured to select a set of samples from the oversampled portion of the data signal, based on the set of phase adjustment signals.

2. A phase-locked loop comprising:

(a) a sample selector configured to select a set of samples from an oversampled portion of a data signal;

(b) a dynamic phase decision control circuit configured to indicate whether a predetermined number of edges is present in the set of samples; and

(c) a phase detector configured to determine a skew condition and a direction of the skew condition of the set of samples based on the indication of the dynamic phase decision control circuit,

wherein said phase detector is configured to produce a set of skew detection signals based on at least one skew condition determination, and wherein said phase-locked loop further comprises a loop filter configured to filter the set of skew detection signals, and

wherein said dynamic phase decision control circuit is also configured to detect an absence of edges in the set of samples, and wherein a state change of the loop filter is inhibited according to the indication of the absence of edges.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2018
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: SK HYNIX INC.
Reel/Frame 045992/0341 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 045925/0124 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2018
From: WEI, SEN-JUNG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 045795/0955 →
SECURITY INTEREST Recorded Jul 25, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 043095/0414 →