Memory register having an integrated delay-locked loop

1. A memory device, comprising:

a plurality of memory chips coupled in series, the first memory chip of the plurality of memory chips being coupled to a first terminal resistance and a last memory chip of the plurality of memory chips being coupled to a second terminal resistance;

a register serially coupled to the memory chips, the register configured to receive an address signal, a control signal, and at least one clock signal; and

an integrated delay-locked loop in the register, the integrated delay-locked loop comprising a phase detector, the phase detector configured to:

receive the at least one clock signal and a delayed clock signal;

compare a phase of the at least one clock signal to a phase of the delayed clock signal;

generate an error signal based on the comparison; and

integrate the error signal to generate a delay control signal and force the error signal to go to zero while maintaining a phase lock between the at least one clock signal and the delayed clock signal.

2. The memory device of claim 1 , wherein the register drives the address signal and the control signal through the memory chips, and the register buffers the at least one clock signal.

3. The memory device of claim 1 , wherein the delay-locked loop receives the at least one clock signal and outputs the delayed clock signal having a predetermined delay.

4. The memory device of claim 1 , wherein the delay-locked loop further comprises:

a plurality of variable delay gates coupled in series and coupled in parallel to the phase detector, at least one of the plurality of delay gates receiving the at least one clock signal and at least one of the plurality of delay gates outputting the delayed clock signal having a predetermined delay, wherein

the predetermined delay is controlled by the delay control signal.

5. The memory device of claim 4 , wherein the memory device has an associated dynamic phase offset, and the delay-locked loop reduces the timing of the dynamic phase offset.

6. The memory device of claim 1 , wherein the memory chips comprise dynamic random access memory (DRAM) chips.

7. The memory device of claim 1 , wherein the memory device comprises a registered dual in-line memory module (RDIMM).

8. The memory device of claim 1 , wherein the memory device is a double data rate type 3 (DDR3) memory device.

9. A processing system, comprising:

a processor; and

a random access memory device coupled to the processor through a bus, the random access memory device comprising:

a plurality of memory chips coupled in series, the first memory chip of the plurality of memory chips being coupled to a first terminal resistance and a last memory chip of the plurality of memory chips being coupled to a second terminal resistance

at least one register coupled to the plurality of memory chips the register configured to receive an address signal, a control signal, and at least one clock signal; and; and

a delay-locked loop integrated in the register, the delay-locked loop comprising a phase detector, the phase detector configured to:

receive the at least one clock signal and a delayed clock signal;

compare a phase of the at least one clock signal to a phase of the delayed clock signal;

generate an error signal based on the comparison; and

integrate the error signal to generate a delay control signal and force the error signal to go to zero while maintaining a phase lock between the at least one clock signal and the delayed clock signal.

10. The processing system of claim 9 , wherein the random access memory device further comprises:

a plurality of memory chips coupled in series, the register being coupled in series to at least one of the memory chips.

11. The processing system of claim 10 , wherein the memory chips comprise dynamic random access memory (DRAM) chips.

12. The processing system of claim 9 , wherein the at least one register drives the address signal and the control signal through the memory chips, and the register buffers the at least one clock signal.

13. The processing system of claim 9 , wherein the delay-locked loop receives the at least one clock signal and outputs the delayed clock signal having a predetermined delay.

14. The processing system of claim 9 , wherein the delay-locked loop comprises;

a plurality of variable delay gates coupled in series and coupled in parallel to the phase detector, at least one of the plurality of delay gates receiving the at least one clock signal and at least one of the plurality of delay gates outputs the delayed clock signal having a predetermined delay, wherein

the predetermined delay is controlled by the delay control signal.

15. The processing system of claim 14 , wherein the random access memory device has an associated dynamic phase offset, and the delay-locked loop reduces the timing of the dynamic phase offset.

16. The processing system of claim 9 , wherein the random access memory device comprises a registered dual in-line memory module (RDIMM).

17. A method for improving timing budgets in a registered dual in-line memory module (RDIMM) having a register which receives an input clock signal, the method comprising:

providing a delay-locked loop in the register;

receiving the input clock signal in the delay-locked loop;

outputting an output clock signal from the delay-locked loop;

comparing, in a phase detector of the register, a phase of the output clock signal to a phase of the input clock signal;

generating an error signal based on the comparison;

integrating, in the phase detector, the error signal to generate a delay control signal, wherein integrating the error signal forces the error signal to go to zero while maintaining a phase lock between the input clock signal and the output clock signal; and

delaying the output clock signal by a predetermined amount based on the control signal.