High frequency fractional-N divider
View Patent ↗A divider can include a phase selection circuit that switches between a plurality of phase-separated clock signals in response to a fractional control signal to form a selected clock signal, the selected clock signal being utilized to generate a second clock signal; and a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the transition control signal indicating when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal.
1. A frequency divider comprising:
a phase selection circuit that switches between a plurality of phase-separated signals in response to a fractional control signal to generate a second clock signal;
a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the fractional control signal providing when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal; and
a plurality of high-speed prescalers that receive a plurality of high-frequency phase-separated signals having an identical frequency and generate the plurality of phase-separated clock signals that are at a lower frequency based on the transition control signal from the counter, the plurality of high-speed prescalers being coupled to provide the plurality of phase-separated clock signals to the phase selection circuit, wherein:
the phase-selection circuit generates the second clock signal based on the plurality of the lower frequency phase-separated clock signals; and
the plurality of high-speed prescalers further includes:
a first high-speed prescaler receiving a first high-frequency signal and transmitting a first phase separated clock signal;
a second prescaler receiving a second high-frequency signal and transmitting a second phase-separated clock signal; and
a third prescaler receiving a third high-frequency signal and transmitting a third phase separated clock signal;
wherein the first, the second, and the third prescalers and the counter are set to count a reduced number of cycles “N” to adjust a time period of the divided signal, where N is an integer greater than or equal to 1; and
wherein a divide-by-N+⅓ function is achieved by switching between the first clock signal, the second clock signal, and the third clock signal in turn after the reduced number of cycles of one of the plurality of high-frequency signals.
2. A frequency divider comprising:
a phase selection circuit that switches between a plurality of phase-separated signals in response to a fractional control signal to generate a second clock signal;
a counter that receives the second clock signal and generates the fractional control signal and a transition control signal, the fractional control signal providing when the second clock signal should switch states in response to a transition of the selected clock signal, the counter generating a feed-back clock signal; and
a plurality of high-speed prescalers that receive a plurality of high-frequency phase-separated signals having an identical frequency and generate the plurality of phase-separated clock signals that are at a lower frequency based on the transition control signal from the counter, the plurality of high-speed prescalers being coupled to provide the plurality of phase-separated clock signals to the phase selection circuit, wherein:
the phase-selection circuit generates the second clock signal based on the plurality of the lower frequency phase-separated clock signals; and
the plurality of high-speed prescalers further includes:
a first high-speed prescaler receiving a first high-frequency signal and transmitting a first phase separated clock signal;
a second prescaler receiving a second high-frequency signal and transmitting a second phase-separated clock signal; and
a third prescaler receiving a third high-frequency signal and transmitting a third phase separated clock signal;
wherein the first, the second, and the third prescalers and the counter are set to count a reduced number of cycles “N” to adjust a time period of the divided signal, where N is an integer greater than or equal to 1; and
wherein a divide-by-N+⅔ function is achieved by alternately switching between the first clock signal, the second clock signal, and the third clock signal in turn after the reduced number of cycles of one of the plurality of high-frequency signals.
3. A method of frequency dividing, comprising:
receiving a plurality of phase-separated clock signals having an identical frequency;
switching between the plurality of phase-separated clock signals in response to a first switch signal to generate a plurality of selected clock signals;
generating a second clock signal based on the selected clock signals in response to a second switch signal; and
generating the first and second switch signals after a number of cycles “N” of one of the plurality of phase separated clock signals;
wherein N is an integer greater than or equal to 1 ; and
wherein the phase-separated clock signals are divided by a number selected from the group consisting of N+⅓, N+⅔, and N+1.
4. The method of claim 3 , wherein the plurality of phase-separated clock signals are high frequency signals and generating the first and second switch signals is achieved after N cycles of one of the plurality of phase-separated clock signals.
5. The method of claim 4 , wherein generating the second clock signal includes:
receiving the selected clock signal into a high-speed prescaler, the high-speed prescaler providing the second clock signal that has lower frequency than the selected clock signal.
6. The method of claim 4 , further including:
receiving a plurality of high-frequency clock signals into a plurality of high-speed prescalers; and
generating the plurality of lower frequency phase-separated clock signals that correspond to the plurality of high frequency clock signals.